Deciphering motherboard post codes. BIOS beeps and BIOS error codes

POST card or POST tester is PCI board extension, which has a digital indicator that displays motherboard initialization codes. Using this code, you can find which of the board components has a malfunction. The codes often depend on the BIOS manufacturer. If there are no errors and the test is successful, then POST produces a code that does not change the value, for example, on most motherboards
When initialization is completed, the code “FF” is displayed. Testers are also often equipped with LEDs that display voltages +5 +3.3 +12, −12.

Here are the error codes suitable for most BIOS versions:

Description:

I bring to your attention the main POST codes forBIOSmanufacturerAMI. A short introduction. Immediately after pressing the POWER button on system unit of a personal computer, control of the PC goes directly to the BIOS. At this time (at the beginning of the PC startup), the processor sends a signal to the BIOS chip, which initializes the loading of the BOOT-ROUTINE firmware of the Basic I/O System.
The BOOT-ROUTINE firmware calls the POST self-test routine.

Subroutine POST (Power-On Self Test) tests the equipment installed on the computer, configures it and prepares it for work.

A separate test is performed for each individual piece of equipment (processor, memory, video card, keyboard, input/output ports, etc.). Each test has its own unique number, which is called a POST code. POST code written to the Manufacturing Test Port (with address 0080H) before running each individual POST test.

After the POST test code is written to the Manufacturing Test Port, the testing procedure for the corresponding equipment begins. If the testing procedure fails, the POST code of the last procedure (which caused the error) remains in the Manufacturing Test Port. If you know the POST code of the last procedure, you can determine the device that caused the error.

Reading POST codes can be done in several ways.

• If your motherboard has a built-in POST code indicator, information about the POST code of the last procedure can be found from it.
• On some systems, the POST code of the last procedure performed may be displayed on the monitor screen during the POST procedure.
• A special expansion card can be used to read POST codes.

Since BIOS is produced by several manufacturers, each BIOS from an individual manufacturer has its own table of POST codes.

This table contains POST codes that are displayed during the full POST procedure.

• CF Detects processor type and tests CMOS read/write
• C0 The chipset and L1-, L2-cache are pre-initialized, the interrupt controller, DMA, timer are programmed
• C1 The type and amount of RAM is detected
• C3 BIOS code is unpacked into a temporary area of ​​RAM
• 0C BIOS checksums are checked
• C5 BIOS code is copied to shadow memory and control is transferred to the Boot Block module
• 01 XGROUP module is unpacked at physical address 1000:0000h
• 02 Processor initialization. The CR and MSR registers are set
• 03 I/O resources are determined (Super I/O)
• 05 Clears screen and CMOS status flag
• 06 Coprocessor is being checked
• 07 Keyboard controller is identified and tested
• 08 Keyboard interface is detected
• 09 Initializing the Serial ATA controller
• OA Detects the keyboard and mouse that are connected to the PS/2 ports
• 0B AC97 audio controller resources are being installed
• OE Testing memory segment F000h
• 10 The type of flash memory is determined
• 12 CMOS tested
• 14 Set values ​​for chipset registers
• 16 The clock generator is initially initialized
• 18 The type of processor, its parameters and L1 and L2 cache sizes are determined
• 1B The interrupt vector table is initialized
• 1C Checks CMOS checksums and battery voltage
• 1D Power Management System Defined
• 1F Loads the keyboard matrix (for laptops)
• 21 The Hardware Power Management system is initializing (for laptops)
• 23 Math coprocessor, disk drive, chipset initialization are tested
• 24 The processor microcode is being updated. Creates a resource distribution map for Plug and Play devices
• 25 Initial PCI initialization: lists devices, searches for VGA adapter, writes VGA BIOS to C000:0
• 26 The clock frequency is set according to CMOS Setup. Synchronization of unused DIMM and PCI slots is disabled. The monitoring system (H/W Monitor) is initialized
• 27 Interrupt INT 09h enabled. The keyboard controller is initialized again
• 29 MTRR registers are programmed, APIC is initialized. The IDE controller is being programmed. The processor frequency is measured. The video system BIOS extension is called
• 2B Search for video adapter BIOS
• 2D The Award splash screen is displayed, information about the processor type and its speed
• 33 Keyboard reset
• 35 First DMA channel being tested
• 37 Second DMA channel being tested
• 39 DMA page registers are tested
• 3C Configuring 8254 controller (timer)
• 3E Checking the 8259 interrupt controller
• 43 Interrupt controller is checked
• 47 ISA/EISA buses are tested
• 49 The amount of RAM is calculated. Registers are being configured for the AMD K5 processor
• 4E MTRR registers are programmed for Syrix processors. L2 cache and APIC are initialized
• 50 USB bus detected
• 52 The RAM is tested and the results are displayed. Clearing extended memory
• 53 If the CMOS is cleared, the login password is reset
• 55 Displays the number of processors (for multiprocessor platforms)
• 57 The EPA logo is displayed. Initial Initialization of ISA PnP Devices
• 59 Virus protection system is determined
• 5B Prompt for running BIOS update from floppy disk
• 5D Launches Super I/O controller and integrated audio controller
• 60 Entering CMOS Setup if the Delete key was pressed
• 65 PS/2 mouse is initializing
• 69 L2 cache enabled
• 6B Chipset registers are configured according to BIOS Setup
• 6D Assigns resources for ISA PnP devices and COM ports for integrated devices
• 6F Initializes and configures the floppy disk controller
• 75 IDE devices are detected and installed: hard drives, CD/DVD, LS-120, ZIP, etc.
• 76 Information about detected IDE devices is displayed
• 77 Serial and parallel ports are initialized
• 7A The math coprocessor is reset and ready for operation.
• 7C Defines protection against unauthorized writing to hard drives
• 7F If there are errors, a message is displayed and the Delete and F1 keys are pressed
• 82 Memory is allocated for power management and changes are written to the ESCD table.
• The splash screen with the EPA logo is removed. Requests a password if needed
• 83 All data is saved from the temporary stack to CMOS
• 84 Displaying Initializing Plug and Play Cards message
• 85 USB initialization complete
• 87 SYSID tables are created in the DMI area
• 89 ACPI tables are being installed. Interrupts are assigned to PCI devices
• 8B Called by the BIOS of additional ISA or PCI controllers, with the exception of the video adapter
• 8D Sets RAM parity parameters using CMOS Setup. APM is initialized
• 8F IRQ 12 is allowed for hot plugging of a PS/2 mouse
• 94 Completion of chipset initialization. Displays the resource allocation table. Enable L2 cache. Setting the summer/winter time transition mode
• 95 Sets the keyboard auto-repeat frequency and Num Lock state
• 96 For multiprocessor systems, registers are configured (for Cyrix processors). The ESCD table is created. The DOS Time timer is set according to the RTC CMOS clock. Boot device partitions are saved for use by the built-in antivirus. The speaker announces the end of POST. The MSIRQ FF table is created. The BIOS interrupt INT 19h is executed. Search for the bootloader in the first sector of the boot device

A shortened procedure is performed by setting the Quick Power On Self Test option in the BIOS.

• 65 The video adapter is being reset. The sound controller and input/output devices are initialized, the keyboard and mouse are tested. BIOS integrity is checked
• 66 Cache is initializing. An interrupt vector table is created. The power management system is initializing
• 67 The CMOS checksum is checked and the battery is tested. The chipset is configured based on CMOS parameters
• 68 Video adapter is initializing
• 69 Configuring the interrupt controller
• 6A Testing RAM (accelerated)
• 6B Displays EPA logo, CPU and memory test results
• 70 A prompt to enter BIOS Setup is displayed. A mouse connected to PS/2 or USB is initialized
• 71 Cache controller is initializing
• 72 Chipset registers are being configured. A list of Plug and Play devices is created.& The drive controller is initialized
• 73 Hard disk controller is initializing
• 74 Coprocessor is initializing
• 75 If necessary, the hard drive is write-protected
• 77 If necessary, a password is requested and messages Press F1 to continue, DEL to enter Setup are displayed
• 78 Expansion cards with their own BIOS are initialized
• 79 Platform resources are initializing
• 7A The root table RSDT, device tables DSDT, FADT, etc. are generated.
• 7D Collects information about boot device partitions
• 7E BIOS is preparing to boot the operating system
• 7F The NumLock indicator status is set according to the settings
• BIOS Setup
• 80 INT 19 is called and the operating system is started

AMIBIOS8.0

• D0 Initialization of the processor and chipset. Checking BIOS boot block checksums
• D1 Initialization of I/O ports. The command for the BAT self-test is sent to the keyboard controller
• D2 Disable L1/L2 cache. The amount of installed RAM is determined
• D3 Memory regeneration schemes are configured. Allowed to use cache memory
• D4 Test 512 KB memory. The stack is installed and the communication protocol with the cache memory is assigned
• D5 BIOS code is unpacked and copied to shadow memory
• D6 Checks BIOS checksums and pressing Ctrl+Home keys (BIOS recovery)
• D7 Control is transferred to the interface module, which unpacks the code into the Run-Time area
• D8 The executable code is unpacked from flash memory into operational memory. CPUID information is saved
• D9 The unpacked code is transferred from the temporary storage area to segments 0E000h and 0F000h of RAM
• DA CPUID registers are restored. POST execution is moved to RAM
• E1–E8, EC–EE Configuration related errors system memory
• 03 Processing of NMI, parity errors, and output of signals to the monitor is prohibited. An area is reserved for the GPNV event log, the initial values ​​of variables from the BIOS are set
• 04 Checks battery health and calculates CMOS checksum
• 05 The interrupt controller is initialized and the vector table is built
• 06 The timer is being tested and prepared for operation
• 08 Keyboard testing (keyboard lights flashing)
• C0 Initial processor initialization. Do not use cache memory. Defined by APIC
• C1 For multiprocessor systems, the processor responsible for starting the system is determined
• C2 Completes the assignment of the processor to start the system. Identification using CPUID
• C5 The number of processors is determined and their parameters are configured
• C6 Initializes cache memory for faster POST.
• C7 Processor initialization completes
• 0A Keyboard controller detected
• 0B Search for a mouse connected to the PS/2 port
• 0C Checking for keyboard presence
• 0E Various input devices are detected and initialized
• 13 Initial initialization of chipset registers
• 24 Platform-specific BIOS modules are unpacked and initialized.
• An interrupt vector table is created and interrupt processing is initialized
• 2A The DIM mechanism identifies devices on local buses. The video adapter is being prepared for initialization, a resource distribution table is being built
• 2C Detection and initialization of the video adapter, the video adapter is called by the BIOS
• 2E Finding and initializing additional I/O devices
• 30 Prepares for SMI processing
• 31 ADM module is initialized and activated
• 33 The simplified loading module is initializing
• 37 Displays AMI logo, BIOS version, processor version, key prompt to enter BIOS
• 38 Using DIM, various devices on local buses are initialized
• 39 DMA controller is initializing
• 3A Sets the system time according to the RTC clock
• 3B RAM is tested and results are displayed
• 3C Chipset registers are configured
• 40 Serial and parallel ports, mathematical coprocessor, etc. are initialized.
• 52 Based on the results of the memory test, the RAM data in CMOS is updated
• 60 BIOS Setup sets the NumLock state and configures auto-repeat parameters
• 75 The procedure for working with disk devices is started (interrupt INT 13h)
• 78 A list of IPL devices is created (from which the operating system can be loaded)
• 7C ESCD extended system configuration tables are created and written to NVRAM
• 84 Log errors encountered during POST
• 85 Messages are displayed about detected non-critical errors.
• 87 If necessary, BIOS Setup is launched, which is first unpacked into RAM
• 8C Chipset registers are configured in accordance with BIOS Setup
• 8D ACPI tables are built
• 8E Configures non-maskable interrupt (NMI) service
• 90 SMI is finally initialized
• A1 Clearing data that is not needed when loading the operating system
• A2 EFI modules are prepared to interact with the operating system
• A4 In accordance with the BIOS Setup language module is initialized
• A7 The POST procedure summary table is displayed
• A8 Sets the state of the MTRR registers
• A9 If necessary, waits for keyboard commands to be entered
• AA Removes POST interrupt vectors (INT 1Ch and INT 09h)
• AB Devices for loading the operating system are detected
• AC The final stages of setting up the chipset in accordance with BIOS Setup
• B1 ACPI interface is configured
• 00 Interrupt processing INT 19h is called (boot sector search, OS loading)

Phoenix Bios 4.0

• 02 Verify Real Mode
• 03 Disable Non-Maskable Interrupt (NMI)
• 04 Get CPU type
• 06 Initialize system hardware
• 08 Initialize chipset with initial POST values
• 09 Set IN POST flag
• 0A Initialize CPU registers
• 0B Enable CPU cache
• 0C Initialize caches to initial POST values
• 0E Initialize I/O component
• 0F Initialize the local bus IDE
• 10 Initialize Power Management
• 11 Load alternate registers with initial POST values
• 12 Restore CPU control word during warm boot
• 13 Initialize PCI Bus Mastering devices
• 14 Initialize keyboard controller
• 16 (1-2-2-3) BIOS ROM checksum
• 17 Initialize cache before memory autosize
• 18 8254 timer initialization
• 1A 8237 DMA controller initialization
• 1C Reset Programmable Interrupt Controller
• 20 (1-3-1-1) Test DRAM refresh
• 22 (1-3-1-3) Test 8742 Keyboard Controller
• 24 Set ES segment register to 4 GB
• 26 Enable A20 line
• 28 Autosize DRAM
• 29 Initialize POST Memory Manager
• 2A Clear 512 KB base RAM
• 2C (1-3-4-1) RAM failure on address line xxxx
• 2E (1-3-4-3) RAM failure on data bits xxxx of low byte of memory bus
• 2F Enable cache before system BIOS shadow
• 30 (1-4-1-1) RAM failure on data bits xxxx of high byte of memory bus
• 32 Test CPU bus-clock frequency
• 33 Initialize Phoenix Dispatch Manager
• 34 Disable Power Button during POST
• 35 Re-initialize registers
• 36 Warm start shut down
• 37 Re-initialize chipset
• 38 Shadow system BIOS ROM
• 39 Re-initialize cache
• 3A Autosize cache
• 3C Advanced configuration of chipset registers
• 3D Load alternate registers with CMOS values
• 40 CPU speed detection
• 42 Initialize interrupt vectors
• 45 POST device initialization
• 46 (2-1-2-3) Check ROM copyright notice
• 48 Check video configuration against CMOS
• 49 Initialize PCI bus and devices
• 4A Initialize all video adapters in system
• 4B QuietBoot start (optional)
• 4C Shadow video BIOS ROM
• 4E Display BIOS copyright notice
• 50 Display CPU type and speed
• 51 Initialize EISA board
• 52 Test keyboard The keyboard is being tested
• 54 Set key click if enabled
• 55 Initialize USB bus
• 58 (2-2-3-1) Test for unexpected interrupts
• 59 Initialize POST display service
• 5A Display prompt “Press F2 to enter SETUP”
• 5B Disable CPU cache
• 5C Test RAM between 512 and 640 KB
• 60 Test extended memory
• 62 Test extended memory address lines
• 64 Jump to UserPatch1
• 66 Configure advanced cache registers
• 67 Initialize Multi Processor APIC
• 68 Enable external and CPU caches
• 69 Setup System Management Mode (SMM) area
• 6A Display external L2 cache size
• 6B Load custom defaults (optional)
• 6C Display shadow-area message
• 6E Display possible high address for UMB recovery
• 70 Display error messages Error messages are displayed
• 72 Check for configuration errors
• 76 Check for keyboard errors
• 7C Set up hardware interrupt vectors
• 7D Initialize hardware monitoring
• 7E Initialize coprocessor if present
• 80 Disable onboard Super I/O ports and IRQs
• 81 Late POST device initialization
• 82 Detect and install external RS232 ports
• 83 Configure non-MCD IDE controllers
• 84 Detect and install external parallel ports
• 85 Initialize PC-compatible PnP ISA devices
• 86 Re-initialize onboard I/O ports
• 87 Configure Motheboard Configurable Devices (optional)
• 88 Initialize BIOS Data Area
• 89 Enable Non-Maskable Interrupts (NMIs)
• 8A Initialize Extended BIOS Data Area
• 8B Test and initialize PS/2 mouse
• 8C Initialize floppy controller
• 8F Determine number of ATA drives (optional)
• 90 Initialize hard-disk controllers
• 91 Initialize local-bus harddisk controllers
• 92 Jump to UserPatch2
• 93 Build MPTABLE for multi-processor boards
• 95 Install CD ROM for boot
• 96 Clear huge ES segment register
• 97 Fixup Multi Processor table
• 98 (1-2) Search for option ROMs. One long, two short beeps on checksum failure
• 99 Check for SMART Drive (optional)
• 9A Shadow option ROMs
• 9C Set up Power Management
• 9D Initialize security engine (optional)
• 9E Enable hardware interrupts
• 9F Determine number of ATA and SCSI drives
• A0 Set time of day
• A2 Check key lock
• A4 Initialize Typematic rate
• A8 Erase F2 prompt
• AA Scan for F2 key stroke
• AC Enter SETUP
• AE Clear Boot flag
• B0 Check for errors
• B2 POST done – prepare to boot operating system
• B4 (1) One short beep before boot
• B5 Terminate QuietBoot (optional)
• B6 Check password (optional)
• B9 Prepare Boot
• BA Initialize DMI parameters
• BB Initialize PnP Option ROMs
• BC Clear parity checkers
• BD Display MultiBoot menu
• BE Clear screen (optional)
• BF Check virus and backup reminders
• C0 Try to boot with INT 19
• C1 Initialize POST Error Manager (PEM)
• C2 Initialize error logging
• C3 Initialize error display function
• C4 Initialize system error handler
• C5 PnPnd dual CMOS (optional)
• C6 Initialize notebook docking (optional)
• C7 Initialize notebook docking late
• D2 Unknown interrupt
• E0 Initialize the chipset
• E1 Initialize the bridge
• E2 Initialize the CPU
• E3 Initialize system timer
• E4 Initialize system I/O
• E5 Check force recovery boot
• E6 Checksum BIOS ROM
• E7 Go to BIOS
• E8 Set Huge Segment
• E9 Initialize Multi Processor
• EA Initialize OEM special code
• EB Initialize PIC and DMA
• EC Initialize Memory type
• ED Initialize Memory size
• EE Shadow Boot Block
• EF System memory test
• F0 Initialize interrupt vectors
• F1 Initialize Real Time Clock
• F2 Initialize video
• F3 Initialize System Management Mode
• F4 (1) Output one beep before boot
• F5 Boot to Mini DOS
• F6 Clear Huge Segment
• F7 Boot to Full DOS

Original and reliable tables of POST codes can be found on the corresponding websites of BIOS manufacturers: “AMI” and “Award”. Sometimes POST code tables are provided in motherboard manuals.
1. Test of software-accessible processor registers (POST codes: 01, 02).
2. Checking the RAM regeneration period (POST code: 04).
3. Initialize the keyboard controller (POST code: 05).
4. Preliminary check of the performance of non-volatile memory (CMOS) and the condition of the CMOS battery (POST code: 07).
5. Initialization of chipset registers with default values ​​(POST code: BE, hex).
6. Checking the presence and determining the size of RAM (POST code: C1, hex).
7. Determining the presence and size of external cache memory (POST code: C6, hex).
8. Checking the first 64 KB of RAM (POST code: 08).
9. Initialization of interrupt vectors (POST code: 0A, hex).
10. Checking the CMOS checksum (POST code: 0V, hex).
11. Detection and initialization of the video controller (POST code: 0D, hex).
12. Video memory check (POST code: 0E, hex).
13. Checking the BIOS checksum (POST code: 0F, hex).
14. Checking controllers and DMA page registers (POST codes: 10,
11, hex).
15. Checking the system timer (POST code: 14, hex).
16. Checking and initializing interrupt controllers (POST codes: 15...18, hex).
17. Initialization of expansion bus slots (POST codes: 20...2F, hex).
18. Determining the size and checking the main and extended memory (POST codes: 30, 31, hex).
19. Re-initialize the chipset registers in accordance with the values ​​​​set in CMOS Setup (POST code: BF, hex).
20. Initialization of the FDD controller (POST code: 41, hex).
21. Initialization of the HDD controller (POST code: 42, hex).
22. Initialization of COM and LPT ports (POST code: 43, hex).
23. Detection and initialization of the math coprocessor (POST code: 45, hex).
24. Checking whether a password is required (POST code: 4F, ​​hex).
25. Initializing BIOS extensions (POST code: 52, hex).
26. Setting the Virus Protect, Boot Speed, NumLock, Boot Attempt parameters in accordance with the values ​​​​set in CMOS Setup (POST codes: 60...63, hex).
27. Calling the operating system boot procedure (POST code: FF, hex).
As can be seen from the above sequence, the ability to display diagnostic messages on the monitor screen appears only after the video controller is initialized, and if the POST procedure stopped at one of the previous stages, then it is not possible to see at which one.

PI0049

POST card for defect detection of computer motherboards, model PI0049, is designed to display POST codes of all BIOS manufacturers. This product is better known as PC Ana-lyz-er 2, the operating features of which have been repeatedly discussed on the pages of our website. The user manual contains a list of engineering passwords, as well as a list of standard keyboard shortcuts for entering the BIOS. The development of the POST card is protected by patent 01224987.4 (China).

PI0050

POST card IC80 V5.0

QiGuan KLPI6

The KLPI6-SD diagnostic card manufactured by QiGuan Electronics is made in accordance with the international standard IEC 61010-1, which sets the requirements for low-voltage overvoltage test equipment. Functional feature POST cards KLPI6-SD - the ability to display POST codes of a personal computer on an external display panel. In addition to the current code, both indicators display previous values, as well as the POST code of the fatal failure.

QiGuan MKCP6A

The board for diagnosing a personal platform and testing it for stability (Diagnostics and Stability Test Card), model MKCP6A, was developed by QiGuan Electronics using technology protected by national patent 03126857.9 (China). To display POST codes, there are three pairs(!) of indicators on the board: the first pair is designed to display a faulty code, the next pair displays the current POST code, and the last pair displays the previous code.

SL-M04A

A rare version of the user manual in Turkish for the diagnostic POST controller PC Analyzer (PC Analizoru in Turkish). In addition to the well-known descriptions of POST codes, it includes a list of control points from almost all well-known BIOS manufacturers. For convenience, all post codes are sorted by number, making them easier to access and understand. Comments for them follow directly after the code and are separated by the name BIOS.

Analysis of computer errors using a diagnostic card (POST card)

1. Introduction
2. General description of POST card

4. Error code table
5. Description of sound signals
6. Reset a forgotten BIOS password

Introduction

The card is called POST (Power On Self Test - self-test card). Displays error codes when the operating system cannot boot or there is no image on the screen or no BIOS sounds.

When power is applied, the BIOS performs an accurate test of the circuit, memory, keyboard, video card, hard drive, then analyzes the system configuration. After the basic input/output system is initialized, the operating system loads.

The diagnostic card will not display data in the following cases:
1. The card is inserted into the motherboard without a CPU.
2. When the RST LED is lit.

General description of POST card

Description of luminous diodes:

Error Code Table

Description of sound signals

AMI BIOS Fatal Errors

AMI BIOS sound codes (not fatal errors)

Award BIOS beep codes

Phoenix BIOS beep codes

IBM BIOS beep codes

Resetting a forgotten BIOS password

AMI passwords:

Other BIOS:

Reset BIOS password programmatically.

The CMOS ROM can be reset programmatically using the command line with the command debug(Works only up to Windows 7 version, does not work in 8).

Reset Award BIOS password:
C:\>debug
-o 70 34 "Enter"
-o 71 34 "Enter"
-q "Enter"
or
C:\>debug
-o 70 11 "Enter"
-o 71 11 "Enter"
-q "Enter"

Reset AMI BIOS password:
C:\>debug
-o 70 16 "Enter"
-o 71 16 "Enter"
-q "Enter"
or
C:\>debug
-o 70 10 "Enter"
-o 71 0 "Enter"
-q "Enter"

Reset Phoenix BIOS password:
C:\>debug
-o 70 ff "Enter"
-o 71 17 "Enter"
-q "Enter"

What it looks like on the command line:

The BIOS settings will be erased, so the next time the system boots, you may need to change the settings (for example, if your disk startup order is different, then you need to reassign, otherwise the system will not boot).

Hardware reset CMOS BIOS jumper

Usually, completing the first two steps is enough, just return the jumper to its original position. You can simply close the pins with a screwdriver if the jumper is missing. The pins are usually labeled on the motherboard: Clear CMOS, CL_CMOS, CRTC, CCMOS, CL_RTC, Clean CMOS, CMOS ROM Reset. Or you can simply remove the battery.

You can use the universal CMOS De-Animator utility to reset the BIOS settings programmatically. Can save settings to a file and restore them. Download from the official website CMOS De-Animator

And a small sign telling you which keys you can use to enter the BIOS settings:

American Megatrends, Inc. (AMI)

The checkpoints of the POST procedures performed in AMIBIOS were redesigned and supplemented in 1995 and have not undergone significant changes to date. The first description of POST codes or, as AMI calls them, “check points” in their current form appeared in connection with the release of the V6.24 kernel, 07/15/95. Some changes have been made to AMIBIOS V7.0, which are reflected in this document.

Features of performing AMIBIOS startup procedures

If during the startup process the data 55h, AAh appears in the diagnostic port, you should not compare this information with POST codes - we are dealing with a typical test sequence, the task of which is to check the integrity of the data bus.

At the start stage, the output to the diagnostic port of data is specific to each platform. In some implementations, the first code rendered is associated with actions, which AMI calls chipset specific stuff. This procedure is accompanied by outputting the CCh value to port 80h and performing a number of actions to configure the system logic registers. As a rule, the CCh code appears in cases where system logic from Intel is used, built on the basis of the PIIX controller - these are TX, LX, BX chipsets.

Some on-board I/O chips contain an RTC and a keyboard controller, which are disabled at startup. The purpose of the BIOS is to initialize these board resources for further use. In this case, the first start-up procedure associated with setting up the keyboard controller is accompanied by the output of the value 10h, then the RTC is initialized, as evidenced by the appearance of the DDh code in the diagnostic port. It should be noted that failure of at least one of these resources will result in non-start motherboard in general, at the very first stage of POST execution.

On a number of boards, the initialization process begins with the CPU switching to protected mode. In this case, following the first rendered code 43h, the POST execution continues as described in the AMIBIOS documentation - control is transferred to point D0h.

Unpacked initialization procedure codes

Uncompressed Init Code Check Points

Flash ROM rewrite procedure codes

Boot Block Recovery Codes

Unpacked system BIOS codes executed in ShadowRAM

Runtime code is uncompressed in F000 shadow RAM

Features of the Device Initialization Manager

In addition to the above POST codes, messages about events during the execution of Device Initialization Manager (DIM) are output to the diagnostic port. There are several control points that indicate the initialization status of system or local buses.

The information is displayed in word format, the low byte of which coincides with the system POST code, and the high byte indicates the type of initialization procedure being performed. The most significant tetrad in the high byte indicates the type of procedure being executed, and the low tetrad determines the bus topology for its application.

Senior tetrad

Junior tetrad

If a system memory configuration error is detected, the DE code, DF code, and configuration error code are output to port 80h sequentially in an endless loop, which can take the following values:

2. Award BIOS V4.51PG Elite

AwardBIOS V4.51PG Elite

The dynamically developing company Award Software in 1995 proposed a new solution in the field of low-level software at that time - AwardBIOS "Elite", better known as V4.50PG. The control point maintenance mode has not changed either in the widespread version V4.51 or in the rare version V4.60. The suffixes P and G denote, respectively, support for the PnP mechanism and maintenance of energy saving functions (Green Function).

Performing a POST in Shadow RAM

3. Award BIOS V6.0 Medallion

AwardBIOS V6.0 Medallion

The first mention of Award Medallion BIOS, Version 6.0 dates back to May 12, 1999. The structure of the new product remains unchanged, retaining the early (Early), late (Late) and final (System) phases of hardware initialization. Significant changes affected the POST execution algorithms, which was reflected in the new encoding of checkpoints, significantly expanding their scope of application. However, in the new BIOS there was no place for outdated technologies such as EISA, and for this reason a number of POST codes were abolished.

Executing startup POST procedures from ROM

At the early initialization stage, the BIOS program code is executed from the Boot Block in the Flash ROM, and is accompanied by the output of checkpoints 91h...FFh to the diagnostic port

BIOS recovery

Performing a POST in Shadow RAM

Late initialization is performed in RAM and continues until the user menu is called - CMOS Setup. This POST phase is characterized by the use of memory segment E000h, in which the passage of checkpoints from 01h to 7Fh is processed.

Preparing tables, arrays and structures for starting the operating system

Starting with code 82h, POST configures the system according to the CMOS settings. Its final phase is executed from the Shadow RAM area (segment E800h) and ends with the transfer of control to the operating system - code FFh.

A number of processes occurring in the Award Medallion BIOS are designated by special groups of control points. These include:

System Event codes - control points of system events.

Power Management Debug codes are checkpoints that occur during the execution of APM or ACPI services.

System Error codes - messages about fatal errors.

Debug codes for MP system - initialization points for multiprocessor platforms.

Features of accelerated POST passage

To reduce system boot time, the user can select the "Quick Power On Self Test" option in CMOS Setup. In this case, the completion of POST will be accelerated by refusing to perform some procedures (Quick Boot).

The Quick Boot operating pattern replaces the late and final POST phases and does not affect the operation of the boot block. Award Software offers a codification of the executable expedited POST procedures that differs from the standard one. Quick Boot begins with the output of checkpoint 65h to the diagnostic port and ends with POST code 80h. Then control is transferred to the operating system with the usual Award BIOS code FFh displayed.

Performing a POST in Power Saving Mode

One of the platform states, when the contents of RAM are stored on the hard disk, is called Hibernate. In the ACPI specification ("Advanced Configuration and Power Interface Specification", Revision 2.0a dated 03/31/2002) it is defined as the S4 (Non-Volatile Sleep) power saving mode. Returning to full function requires a special way of completing POST.

The ACPI S4 operating scheme, as with the accelerated start, replaces the late and final phases of POST. An important point is checking the startup script in the boot block. Depending on what ACPI state the system is in after the hardware Reset signal, a decision is made to exit state S4, which begins with the output of test point 90h to the diagnostic port and ends with POST code 9Fh.

4. Phoenix BIOS 4.0 Release 6.0

Phoenix Technologies, Ltd.

One of the leaders in low-level software development, Phoenix Technologies, has released a new version of PhoenixBIOS 4.0 to coincide with the release of Windows95. Support for the Intel Pentium processor family is reflected in the names of the intermediate revisions. One of the latest - Release 6.0 - formed the basis for all released BIOS. With the advent of Release 6.1, there were no significant changes in the execution of POST procedures, and, therefore, this did not affect the indication of checkpoints.

A distinctive feature of PhoenixBIOS is that if during the POST execution errors occur when testing 512 KB of main memory (codes 2Ch, 2Eh, 30h), additional information is output to port 80h in word format, the bits of which identify the failed address line or data cell. For example, the code "2C 0002" means that a memory fault has been detected on address line 1. The code "2E 1020" in this case will mean that a fault has been detected on data lines 12 and 5 in the low byte of the memory data bus. On 386SX systems that use a sixteen-bit data bus, an error cannot occur during code execution step 30h

The POST code output to the diagnostic port is accompanied by an audio signal output to the system speaker. The sound signal generation scheme is as follows:

• The eight-bit code is converted into four two-bit groups
• The value of each group increases by one
• Based on the received value, a short sound signal is generated (for example: code 16h = 00 01 01 10 = 1-2-2-3)

Executing startup POST procedures from ROM

Fatal Error Messages

D0 Error caused by an exceptional situation (Exception error) D2 Calling an interrupt handling procedure from an unidentified source D4 Error associated with a violation of the protocol for issuing and clearing interrupt requests D6 Exiting protected mode with software reset generation D7 To save the state of the video adapter, more is required amount of memory than is available in SMRAM D8 Error during software generation of the processor reset pulse DA Loss of control when returning to Real Mode DC Exit from protected mode with software reset generation without re-initializing the interrupt controller DD Error when testing extended memory DE Keyboard controller error DF Line control error A20 19

Executing procedures from Boot Block

5. Insyde BIOS Mobile Pro

Insyde Software Corp.

The mobile systems market insider has firmly established itself in areas where loyalty to tradition and a conservative approach to BIOS design is required. Having inherited the source code from SystemSoft, the company is constantly working to improve it. The latest revision of MobilePRO is actively used in Mitac and Clevo laptops, the documentation for which formed the basis of the Error Codes table - this is what Insyde Software calls POST checkpoints.

Boot block checkpoints

Despite the fact that Insyde Software created its first BIOS in 1992, the established model of the boot block - or Boot Loader, as the creators themselves called it - was finally formed only by the end of 1995. From this moment on, the starting procedure was numbered by version and creation date.

The most significant point from the point of view of a service engineer examining the loading process computer system with InsydeBIOS, the device becomes a diagnostic code display device. Although, as a rule, Boot Loader uses Manufacture's Diagnostic Port 80h, standard in such cases, in some cases, test point output is performed only on the PIO Port (Parallel Input/Output port for diagnostic purpose), which is nothing more than a parallel port 378h There are implementations in which diagnostic codes sent to port 80h are duplicated to the parallel port.

Executing POSTs from RAM

The most modern InsydeBIOS solutions use 16-bit checkpoint mapping. This is done using ports 80h and 81h, the latter of which is intended to extend standard diagnostics.

The study of control points is made difficult by their irregular construction, when processes of different meaning are accompanied by the same codes. In dual diagnostic systems, there are heterogeneities of a different order: some POST codes are mapped only to one of the ports without the usual duplication in such cases.