What is a post code? New generation of POST cards
Error Message | Description |
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System is booting properly |
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BIOS ROM checksum error | The contents of the BIOS ROM to not match the expected contents. If possible, reload the BIOS from the PAQ |
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Check the video adapter and ensure it"s seated properly. If possible, replace the video adapter |
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7 beeps (1 long, 1s, 1l, 1 short, pause, 1 long, 1 short, 1 short) | The AGP video card is faulty. Reseat the card or replace it outright. This beep pertains to Compaq Deskpro systems |
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1 long never ending beep | Memory error. Bad RAM. Replace and test | |
Reseat RAM then retest; replace RAM if failure continues |
Error Message | Description |
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System is booting properly |
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Initialization error | Error code is displayed |
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System board error | ||
Video adapter error | ||
EGA/VGA adapter error | ||
3270 keyboard adapter error | ||
Power supply error | Replace the power supply |
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Power supply error | Replace the power supply |
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Replace the power supply |
Beeps/Error | Description |
Continuous beeping | System board failure |
One beep; Unreadable, blank or flashing LCD | LCD connector problem; LCD backlight inverter failure; video adapter faulty; LCD assembly faulty; System board failure; power supply failure |
One beep; Message "Unable to access boot source" | Boot device failure; system board failure |
One long, two short beeps | System board failure; Video adapter problem; LCD assembly failure |
One long, four short beeps | Low battery voltage |
One beep every second | Low battery voltage |
Two short beeps with error codes | POST error message |
System board failure |
IBM Intellistation BIOS:
Beep error code: | Action / Run diagnostics on the following components: |
1-1-3 CMOS read/write error | 1.Run Setup 2.System Board |
1-1-4 ROM BIOS check error | 1.System Board |
1-2-X DMA error | 1.System Board |
1-3-X | 1.Memory Module 2.System Board |
1-4-4 | 1. Keyboard 2.System Board |
1-4-X Error detected in first 64 KB of RAM. | 1.Memory Module 2.System Board |
2-1-1, 2-1-2 | 1.Run Setup 2.System Board |
2-1-X First 64 KB of RAM failed. | 1.Memory Module 2.System Board |
2-2-2 | 2.System Board |
2-2-X First 64 KB of RAM failed. | 1.Memory Module 2.System Board |
2-3-X | 1.Memory Module 2.System Board |
2-4-X | 1.Run Setup 2. Memory Module 3.System Board |
3-1-X DMA register failed. | 1.System Board |
3-2-4 Keyboard controller failed. | 1.System Board 2. Keyboard |
3-3-4 Screen initialization failed. | 1. Video Adapter (if installed) 2.System Board 3.Display |
3-4-1 Screen retrace detected an error. | 1. Video Adapter (if installed) 2.System Board 3.Display |
3-4-2 POST is searching for video ROM. | 1. Video Adapter (if installed) 2.System Board |
4 | 1. Video Adapter (if installed) 2.System Board |
All other beep code sequences. | 1.System Board |
One long and one short beep during POST. Base 640 KB memory error or shadow RAM error. | 1.Memory Module 2.System Board |
One long beep and two or three short beeps during POST.(Video error) | 1. Video Adapter (if installed) 2.System Board |
Three short beeps during POST. | 1. See "System board memory" on page 62. 2.System Board |
Continuous beep. | 1.System Board |
Repeating short beeps. | 1. Keyboard stuck key? 2.Keyboard Cable 3.System Board |
Error Message | Description |
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System is booting normally |
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Video adapter error | The video adapter is either faulty or not seated properly. Check the adapter |
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Keyboard controller error | The keyboard controller IC is faulty. Replace the IC if possible |
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The keyboard controller IC is faulty or the keyboard is faulty. Replace the keyboard, if problem still persists, replace the keyboard controller IC |
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The programmable interrupt controller is faulty. Replace the IC if possible |
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The programmable interrupt controller is faulty. replace the IC if possible |
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DMA page register error | The DMA controller IC is faulty. Replace the IC if possible |
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RAM refresh error | ||
RAM parity error | ||
DMA controller 0 error | The DMA controller IC for channel 0 has failed |
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The CMOS RAM has failed |
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DMA controller 1 error | The DMA controller IC for channel 1 has failed |
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CMOS RAM battery error | The CMOS RAM battery has failed. If possible, replace the CMOS or battery |
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CMOS RAM checksum error | The CMOS RAM has failed. If possible, replace the CMOS |
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BIOS ROM checksum error | The BIOS ROM has failed. If possible replace the BIOS or upgrade it |
Error Message | Description |
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System is booting normally |
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Video adapter failure | Either the video adapter is faulty, not seated properly or is missing |
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1 long, 1 short, 1 long | Keyboard controller error | Either the keyboard controller IC is faulty or the system board circuitry is faulty |
1 long, 2 short, 1 long | Either the keyboard controller is faulty or the system board circuitry is faulty |
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1 long, 3 short, 1 long | ||
1 long 4 short, 1 long | The programmable interrupt controller IC is faulty |
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1 long, 5 short, 1 long | DMA page register error | The DMA controller IC 1 or 2 is faulty or the system board circuitry is faulty |
1 long, 6 short, 1 long | RAM refresh error | |
1 long, 7 short, 1 long | ||
1 long, 8 short, 1 long | RAM parity error |
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1 long, 9 short, 1 long | DMA controller 1 error | The DMA controller for channel 0 is faulty or the system board circuitry is faulty |
1 long, 10 short, 1 long | Either the CMOS RAM is faulty. Replace the CMOS |
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1 long, 11 short, 1 long | DMA controller 2 error | The DMA controller for channel 1 is faulty or the system board circuitry is faulty |
1 long, 12 short, 1 long | CMOS RAM battery error | The CMOS RAM battery is faulty or the CMOS RAM is bad. Replace the battery if possible |
1 long, 13 short, 1 long | CMOS checksum error | The CMOS RAM is faulty |
1 long 14 short, 1 long | BIOS ROM checksum failure | The BIOS ROM checksum is faulty. Replace the BIOS or upgrade |
Phoenix ISA/MCA/EISA BIOS:
The beep codes are represented in the number of beeps. E.g. 1-1-2 would mean 1 beep, a pause, 1 beep, a pause, and 2 beeps.
- With a Dell computer, a 1-2 beep code can also indicate that a bootable add-in card is installed but no boot device is attached. For example, in you insert a Promise Ultra-66 card but do not connect a hard drive to it, you will get the beep code. I verified this with a SIIG (crap -- avoid like the plague) Ultra-66 card, and then confirmed the results with Dell.
Error Message | Description |
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CPU test failure | The CPU is faulty. Replace the CPU |
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System board select failure | The motherboard is having an undetermined fault. Replace the motherboard |
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CMOS read/write error | The real time clock/CMOS is faulty. Replace the CMOS if possible |
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Extended CMOS RAM failure | The extended portion of the CMOS RAM has failed. Replace the CMOS if possible |
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BIOS ROM checksum error | The BIOS ROM has failed. Replace the BIOS or upgrade if possible |
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The programmable interrupt timer has failed. Replace if possible |
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DMA read/write failure | The DMA controller has failed. Replace the IC if possible |
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RAM refresh failure | The RAM refresh controller has failed |
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64KB RAM failure | The test of the first 64KB RAM has failed to start |
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First 64KB RAM failure | The first RAM IC has failed. Replace the IC if possible |
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First 64KB logic failure | The first RAM control logic has failed |
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Address line failure | The address line to the first 64KB RAM has failed |
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Parity RAM failure | The first RAM IC has failed. Replace if possible |
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EISA fail-safe timer test | Replace the motherboard |
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EISA NMI port 462 test | Replace the motherboard |
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64KB RAM failure | Bit 0; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 1; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 2; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 3; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 4; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 5; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 6; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 7; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 8; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 9; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 10; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 11; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 12; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 13; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 14; This data bit on the first RAM IC has failed. Replace the IC if possible |
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64KB RAM failure | Bit 15; This data bit on the first RAM IC has failed. Replace the IC if possible |
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Slave DMA register failure | The DMA controller has failed. Replace the controller if possible |
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Master DMA register failure | The DMA controller had failed. Replace the controller if possible |
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Master interrupt mask register failure | ||
Slave interrupt mask register failure | The interrupt controller IC has failed |
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Interrupt vector error | The BIOS was unable to load the interrupt vectors into memory. Replace the motherboard |
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Keyboard controller failure | ||
CMOS RAM power bad | Replace the CMOS battery or CMOS RAM if possible |
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CMOS configuration error | The CMOS configuration has failed. Restore the configuration or replace the battery if possible |
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Video memory failure | There is a problem with the video memory. Replace the video adapter if possible |
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Video initialization failure | There is a problem with the video adapter. Reseat the adapter or replace the adapter if possible |
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The system's timer IC has failed. Replace the IC if possible |
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Shutdown failure | The CMOS has failed. Replace the CMOS IC if possible |
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Gate A20 failure | The keyboard controller has failed. Replace the IC if possible |
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Unexpected interrupt in protected mode | This is a CPU problem. Replace the CPU and retest |
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RAM test failure | System RAM addressing circuitry is faulty. Replace the motherboard |
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Interval timer channel 2 failure | The system timer IC has failed. Replace the IC if possible |
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Time of day clock failure | The real time clock/CMOS has failed. Replace the CMOS if possible |
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Serial port failure | A error has occurred in the serial port circuitry |
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Parallel port failure | A error has occurred in the parallel port circuitry |
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Math coprocessor failure | The math coprocessor has failed. If possible, replace the MPU |
Description |
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Verify real mode |
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Initialize system hardware |
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Initialize chipset registers with initial values |
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Set in POST flag |
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Initialize CPU registers |
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Initialize cache to initial values |
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Initialize power management |
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Load alternative registers with initial POST values |
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Jump to UserPatch0 |
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Initialize timer initialization |
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8254 timer initialization |
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8237 DMA controller initialization |
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Reset Programmable Interrupt Controller |
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Test DRAM refresh |
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Test 8742 Keyboard Controller |
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Set ES segment register to 4GB |
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Clear 512K base memory |
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Test 512K base address lines |
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Test 51K base memory |
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Test CPU bus-clock frequency |
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CMOS RAM read/write failure (this commonly indicates a problem on the ISA bus such as a card not seated) |
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Reinitialize the chipset |
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Shadow system BIOS ROM |
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Reinitialize the cache |
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Autosize the cache |
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Configure advanced chipset registers |
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Load alternate registers with CMOS values |
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Set initial CPU speed |
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Initialize interrupt vectors |
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Initialize BIOS interrupts |
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Check ROM copyright notice |
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Initialize manager for PCI Options ROMs |
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Check video configuration against CMOS |
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Initialize PCI bus and devices |
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initialize all video adapters in system |
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Shadow video BIOS ROM |
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Display copyright notice |
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Display CPU type and speed |
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Set key click if enabled |
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Test for unexpected interrupts |
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Display prompt "Press F2 to enter setup" |
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Test RAM between 512K and 640K |
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Test expanded memory |
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Test extended memory address lines |
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Jump to UserPatch1 |
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Configure advanced cache registers |
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Enable external and CPU caches |
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Initialize SMI handler |
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Display external cache size |
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Display shadow message |
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Display non-disposable segments |
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Display error messages |
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Check for configuration errors |
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Test real-time clock |
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Check for keyboard errors |
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Setup hardware interrupt vectors |
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Test coprocessor if present |
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Disable onboard I/O ports |
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Detect and install external RS232 ports |
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Detect and install external parallel ports |
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Reinitialize onboard I/O ports |
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Initialize BIOS Data Area |
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Initialize Extended BIOS Data Area |
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Initialize floppy controller |
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Initialize hard disk controller |
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Initialize local bus hard disk controller |
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Jump to UserPatch2 |
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Disable A20 address line |
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Clear huge ES segment register |
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Search for option ROMs |
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Shadow option ROMs |
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Setup power management |
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Enable hardware interrupts |
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Scan for F2 keystroke |
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Clear in-POST flag |
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Check for errors |
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POST done - prepare to boot operating system |
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Check password (optional) |
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Clear global descriptor table |
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Clear parity checkers |
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Check virus and backup reminders |
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Try to boot with INT 19 |
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Interrupt handler error |
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Unknown interrupt error |
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Pending interrupt error |
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Initialize option ROM error |
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Extended Block Move |
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Shutdown 10 error |
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Keyboard Controller failure (most likely problem is with RAM or cache unless no video is present) |
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Initialize the chipset |
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Initialize refresh counter |
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Check for Forced Flash |
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Do a complete RAM test |
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Do OEM initialization |
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Initialize interrupt controller |
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Read in bootstrap code |
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Initialize all vectors |
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Initialize the boot device |
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Boot code was read OK |
Quadtel BIOS:
Error Messages | Description |
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System is booting normally |
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The CMOS RAM is faulty. Replace the IC if possible |
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The video adapter is faulty. Reseat the video adapter or replace the adapter if possible |
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Peripheral controller error | One or more of the system peripheral controllers is bad. Replace the controllers and retest |
This table contains POST codes that are displayed during the full POST procedure.
- CF Detects processor type and tests CMOS read/write
- C0 The chipset and L1-, L2-cache are pre-initialized, the interrupt controller, DMA, timer are programmed
- C1 Type and volume detected RAM
- C3 BIOS code is unpacked into a temporary area of RAM
- 0C BIOS checksums are checked
- C5 BIOS code is copied to shadow memory and control is transferred to the Boot Block module
- 01 XGROUP module is unpacked at physical address 1000:0000h
- 02 Processor initialization. The CR and MSR registers are set
- 03 I/O resources are determined (Super I/O)
- 05 Clears screen and CMOS status flag
- 06 Coprocessor is being checked
- 07 Keyboard controller is identified and tested
- 08 Keyboard interface is detected
- 09 Initializing the Serial ATA controller
- OA Detects the keyboard and mouse that are connected to the PS/2 ports
- 0B AC97 audio controller resources are being installed
- OE Testing memory segment F000h
- 10 The type of flash memory is determined
- 12 CMOS tested
- 14 Sets values for chipset registers
- 16 The clock generator is initially initialized
- 18 The type of processor, its parameters and L1 and L2 cache sizes are determined
- 1B The interrupt vector table is initialized
- 1C Checks CMOS checksums and battery voltage
- 1D Power management system is defined
- 1F Loads the keyboard matrix (for laptops)
- 21 The Hardware Power Management system is initializing (for laptops)
- 23 Math coprocessor, disk drive, chipset initialization are tested
- 24 The processor microcode is being updated. Creates a resource distribution map for Plug and Play devices
- 25 Initial PCI initialization: lists devices, searches for VGA adapter, writes VGA BIOS to C000:0
- 26 The clock frequency is set according to CMOS Setup. Synchronization of unused DIMM and PCI slots is disabled. The monitoring system (H/W Monitor) is initialized
- 27 Interrupt INT 09h enabled. The keyboard controller is initialized again
- 29 MTRR registers are programmed, APIC is initialized. The IDE controller is being programmed. The processor frequency is measured. The video system BIOS extension is called
- 2B Search for video adapter BIOS
- 2D The Award splash screen is displayed, information about the processor type and its speed
- 33 Keyboard reset
- 35 First DMA channel being tested
- 37 Second DMA channel being tested
- 39 DMA page registers are tested
- 3C Configuring 8254 controller (timer)
- 3E Checking the 8259 interrupt controller
- 43 Interrupt controller is checked
- 47 ISA/EISA buses are tested
- 49 The amount of RAM is calculated. Registers are configured for AMD processor K5
- 4E MTRR registers are programmed for Syrix processors. L2 cache and APIC are initialized
- 50 USB bus detected
- 52 The RAM is tested and the results are displayed. Clearing extended memory
- 53 If the CMOS is cleared, the login password is reset
- 55 Displays the number of processors (for multiprocessor platforms)
- 57 The EPA logo is displayed. Initial Initialization of ISA PnP Devices
- 59 Virus protection system is determined
- 5B Prompt for running BIOS update from floppy disk
- 5D Launches Super I/O controller and integrated audio controller
- 60 Entering CMOS Setup if the Delete key was pressed
- 65 PS/2 mouse is initializing
- 69 L2 cache enabled
- 6B Chipset registers are configured according to BIOS Setup
- 6D Assigns resources for ISA PnP devices and COM ports for integrated devices
- 6F Initializes and configures the floppy disk controller
- 75 IDE devices are detected and installed: hard drives, CD/DVD, LS-120, ZIP, etc.
- 76 Information about detected IDE devices is displayed
- 77 Serial and parallel ports are initialized
- 7A The math coprocessor is reset and ready for operation.
- 7C Defines protection against unauthorized writing to hard drives
- 7F If there are errors, a message is displayed and the Delete and F1 keys are pressed
- 82 Memory is allocated for power management and changes are written to the ESCD table.
- The splash screen with the EPA logo is removed. Requests a password if needed
- 83 All data is saved from the temporary stack to CMOS
- 84 Displaying Initializing Plug and Play Cards message
- 85 USB initialization complete
- 87 SYSID tables are created in the DMI area
- 89 ACPI tables are being installed. Interrupts are assigned to PCI devices
- 8B Called BIOS additional ISA or PCI controllers, excluding the video adapter
- 8D Sets RAM parity parameters using CMOS Setup. APM is initialized
- 8F IRQ 12 is allowed for hot plugging of a PS/2 mouse
- 94 Completion of chipset initialization. Displays the resource allocation table. Enable L2 cache. Setting the summer/winter time transition mode
- 95 Sets the keyboard auto-repeat frequency and Num Lock state
- 96 For multiprocessor systems, registers are configured (for Cyrix processors). The ESCD table is created. The DOS Time timer is set according to the RTC CMOS clock. Boot device partitions are saved for use by the built-in antivirus. The speaker announces the end of POST. The MSIRQ FF table is created. The BIOS interrupt INT 19h is executed. Search for the bootloader in the first sector of the boot device
A shortened procedure is performed by setting the Quick Power On Self Test option in the BIOS.
- 65 The video adapter is being reset. The sound controller and input/output devices are initialized, the keyboard and mouse are tested. BIOS integrity is checked
- 66 Cache is initializing. An interrupt vector table is created. The power management system is initializing
- 67 The CMOS checksum is checked and the battery is tested. Chipset is configured based on CMOS parameters
- 68 Video adapter is initializing
- 69 Configuring the interrupt controller
- 6A Testing RAM (accelerated)
- 6B Displays EPA logo, CPU and memory test results
- 70 A prompt to enter BIOS Setup is displayed. A mouse connected to PS/2 or USB is initialized
- 71 Cache controller is initializing
- 72 Chipset registers are being configured. A list of Plug and Play devices is created.& The drive controller is initialized
- 73 Hard disk controller is initializing
- 74 Coprocessor is initializing
- 75 If necessary, hard drive write protected
- 77 If necessary, a password is requested and messages Press F1 to continue, DEL to enter Setup are displayed
- 78 Expansion cards with their own BIOS are initialized
- 79 Platform resources are initializing
- 7A The root table RSDT, device tables DSDT, FADT, etc. are generated.
- 7D Collects information about boot device partitions
- 7E BIOS is preparing to boot the operating system
- 7F The NumLock indicator status is set according to the settings
- BIOS Setup
- 80 INT 19 is called and the operating system starts
- D0 Initialization of the processor and chipset. Checking BIOS boot block checksums
- D1 Initialization of I/O ports. The command for the BAT self-test is sent to the keyboard controller
- D2 Disable L1/L2 cache. The amount of installed RAM is determined
- D3 Memory regeneration schemes are configured. Allowed to use cache memory
- D4 Test 512 KB memory. The stack is installed and the communication protocol with the cache memory is assigned
- D5 BIOS code is unpacked and copied to shadow memory
- D6 Checks BIOS checksums and pressing Ctrl+Home keys (BIOS recovery)
- D7 Control is transferred to the interface module, which unpacks the code into the Run-Time area
- D8 The executable code is unpacked from flash memory into operational memory. CPUID information is saved
- D9 The unpacked code is transferred from the temporary storage area to segments 0E000h and 0F000h of RAM
- DA CPUID registers are restored. POST execution is moved to RAM
- E1–E8, EC–EE Errors related to the system memory configuration
- 03 Processing of NMI, parity errors, and output of signals to the monitor is prohibited. An area is reserved for the GPNV event log, the initial values of variables from the BIOS are set
- 04 Checks battery health and calculates CMOS checksum
- 05 The interrupt controller is initialized and the vector table is built
- 06 The timer is being tested and prepared for operation
- 08 Keyboard testing (keyboard lights flashing)
- C0 Initial processor initialization. Do not use cache memory. Defined by APIC
- C1 For multiprocessor systems, the processor responsible for starting the system is determined
- C2 Completes the assignment of the processor to start the system. Identification using CPUID
- C5 The number of processors is determined and their parameters are configured
- C6 Initializes cache memory for faster POST.
- C7 Processor initialization completes
- 0A Keyboard controller detected
- 0B Search for a mouse connected to the PS/2 port
- 0C Checking for keyboard presence
- 0E Various input devices are detected and initialized
- 13 Initial initialization of chipset registers
- 24 Platform-specific BIOS modules are unpacked and initialized.
- An interrupt vector table is created and interrupt processing is initialized
- 2A The DIM mechanism identifies devices on local buses. The video adapter is being prepared for initialization, a resource distribution table is being built
- 2C Detection and initialization of the video adapter, the video adapter is called by the BIOS
- 2E Finding and initializing additional I/O devices
- 30 Prepares for SMI processing
- 31 ADM module is initialized and activated
- 33 The simplified loading module is initializing
- 37 AMI logo, BIOS version, processor version, key prompt to enter BIOS is displayed
- 38 Using DIM, various devices on local buses are initialized
- 39 DMA controller is initializing
- 3A Sets the system time according to the RTC clock
- 3B RAM is tested and results are displayed
- 3C Chipset registers are configured
- 40 Serial and parallel ports, mathematical coprocessor, etc. are initialized.
- 52 Based on the results of the memory test, the RAM data in CMOS is updated
- 60 BIOS Setup sets the NumLock state and configures auto-repeat parameters
- 75 The procedure for working with disk devices is started (interrupt INT 13h)
- 78 A list of IPL devices is created (from which the operating system can be loaded)
- 7C ESCD extended system configuration tables are created and written to NVRAM
- 84 Log errors encountered during POST
- 85 Messages are displayed about detected non-critical errors.
- 87 If necessary, BIOS Setup is launched, which is first unpacked into RAM
- 8C Chipset registers are configured in accordance with BIOS Setup
- 8D ACPI tables are built
- 8E Configures non-maskable interrupt (NMI) service
- 90 SMI is finally initialized
- A1 Clearing data that is not needed when loading the operating system
- A2 EFI modules are prepared to interact with the operating system
- A4 According to BIOS Setup, the language module is initialized
- A7 The POST procedure summary table is displayed
- A8 Sets the state of the MTRR registers
- A9 If necessary, waits for keyboard commands to be entered
- AA Removes POST interrupt vectors (INT 1Ch and INT 09h)
- AB Devices for loading the operating system are detected
- AC The final stages of setting up the chipset in accordance with BIOS Setup
- B1 ACPI interface is configured
- 00 Interrupt processing INT 19h is called (boot sector search, OS loading)
- 02 Verify Real Mode
- 03 Disable Non-Maskable Interrupt (NMI)
- 04 Get CPU type
- 06 Initialize system hardware
- 08 Initialize chipset with initial POST values
- 09 Set IN POST flag
- 0A Initialize CPU registers
- 0B Enable CPU cache
- 0C Initialize caches to initial POST values
- 0E Initialize I/O component
- 0F Initialize the local bus IDE
- 10 Initialize Power Management
- 11 Load alternate registers with initial POST values
- 12 Restore CPU control word during warm boot
- 13 Initialize PCI Bus Mastering devices
- 14 Initialize keyboard controller
- 16 (1-2-2-3) BIOS ROM checksum
- 17 Initialize cache before memory autosize
- 18 8254 timer initialization
- 1A 8237 DMA controller initialization
- 1C Reset Programmable Interrupt Controller
- 20 (1-3-1-1) Test DRAM refresh
- 22 (1-3-1-3) Test 8742 Keyboard Controller
- 24 Set ES segment register to 4 GB
- 26 Enable A20 line
- 28 Autosize DRAM
- 29 Initialize POST Memory Manager
- 2A Clear 512 KB base RAM
- 2C (1-3-4-1) RAM failure on address line xxxx
- 2E (1-3-4-3) RAM failure on data bits xxxx of low byte of memory bus
- 2F Enable cache before system BIOS shadow
- 30 (1-4-1-1) RAM failure on data bits xxxx of high byte of memory bus
- 32 Test CPU bus-clock frequency
- 33 Initialize Phoenix Dispatch Manager
- 34 Disable Power Button during POST
- 35 Re-initialize registers
- 36 Warm start shut down
- 37 Re-initialize chipset
- 38 Shadow system BIOS ROM
- 39 Re-initialize cache
- 3A Autosize cache
- 3C Advanced configuration of chipset registers
- 3D Load alternate registers with CMOS values
- 40 CPU speed detection
- 42 Initialize interrupt vectors
- 45 POST device initialization
- 46 (2-1-2-3) Check ROM copyright notice
- 48 Check video configuration against CMOS
- 49 Initialize PCI bus and devices
- 4A Initialize all video adapters in system
- 4B QuietBoot start (optional)
- 4C Shadow video BIOS ROM
- 4E Display BIOS copyright notice
- 50 Display CPU type and speed
- 51 Initialize EISA board
- 52 Test keyboard The keyboard is being tested
- 54 Set key click if enabled
- 55 Initialize USB bus
- 58 (2-2-3-1) Test for unexpected interrupts
- 59 Initialize POST display service
- 5A Display prompt “Press F2 to enter SETUP”
- 5B Disable CPU cache
- 5C Test RAM between 512 and 640 KB
- 60 Test extended memory
- 62 Test extended memory address lines
- 64 Jump to UserPatch1
- 66 Configure advanced cache registers
- 67 Initialize Multi Processor APIC
- 68 Enable external and CPU caches
- 69 Setup System Management Mode (SMM) area
- 6A Display external L2 cache size
- 6B Load custom defaults (optional)
- 6C Display shadow-area message
- 6E Display possible high address for UMB recovery
- 70 Display error messages Error messages are displayed
- 72 Check for configuration errors
- 76 Check for keyboard errors
- 7C Set up hardware interrupt vectors
- 7D Initialize hardware monitoring
- 7E Initialize coprocessor if present
- 80 Disable onboard Super I/O ports and IRQs
- 81 Late POST device initialization
- 82 Detect and install external RS232 ports
- 83 Configure non-MCD IDE controllers
- 84 Detect and install external parallel ports
- 85 Initialize PC-compatible PnP ISA devices
- 86 Re-initialize onboard I/O ports
- 87 Configure Motheboard Configurable Devices (optional)
- 88 Initialize BIOS Data Area
- 89 Enable Non-Maskable Interrupts (NMIs)
- 8A Initialize Extended BIOS Data Area
- 8B Test and initialize PS/2 mouse
- 8C Initialize floppy controller
- 8F Determine number of ATA drives (optional)
- 90 Initialize hard-disk controllers
- 91 Initialize local-bus harddisk controllers
- 92 Jump to UserPatch2
- 93 Build MPTABLE for multi-processor boards
- 95 Install CD ROM for boot
- 96 Clear huge ES segment register
- 97 Fixup Multi Processor table
- 98 (1-2) Search for option ROMs. One long, two short beeps on checksum failure
- 99 Check for SMART Drive (optional)
- 9A Shadow option ROMs
- 9C Set up Power Management
- 9D Initialize security engine (optional)
- 9E Enable hardware interrupts
- 9F Determine number of ATA and SCSI drives
- A0 Set time of day
- A2 Check key lock
- A4 Initialize Typematic rate
- A8 Erase F2 prompt
- AA Scan for F2 key stroke
- AC Enter SETUP
- AE Clear Boot flag
- B0 Check for errors
- B2 POST done – prepare to boot operating system
- B4 (1) One short beep before boot
- B5 Terminate QuietBoot (optional)
- B6 Check password (optional)
- B9 Prepare Boot
- BA Initialize DMI parameters
- BB Initialize PnP Option ROMs
- BC Clear parity checkers
- BD Display MultiBoot menu
- BE Clear screen (optional)
- BF Check virus and backup reminders
- C0 Try to boot with INT 19
- C1 Initialize POST Error Manager (PEM)
- C2 Initialize error logging
- C3 Initialize error display function
- C4 Initialize system error handler
- C5 PnPnd dual CMOS (optional)
- C6 Initialize notebook docking (optional)
- C7 Initialize notebook docking late
- D2 Unknown interrupt
- E0 Initialize the chipset
- E1 Initialize the bridge
- E2 Initialize the CPU
- E3 Initialize system timer
- E4 Initialize system I/O
- E5 Check force recovery boot
- E6 Checksum BIOS ROM
- E7 Go to BIOS
- E8 Set Huge Segment
- E9 Initialize Multi Processor
- EA Initialize OEM special code
- EB Initialize PIC and DMA
- EC Initialize Memory type
- ED Initialize Memory size
- EE Shadow Boot Block
- EF System memory test
- F0 Initialize interrupt vectors
- F1 Initialize Real Time Clock
- F2 Initialize video
- F3 Initialize System Management Mode
- F4 (1) Output one beep before boot
- F5 Boot to Mini DOS
- F6 Clear Huge Segment
- F7 Boot to Full DOS
American Megatrends, Inc. (AMI)
The checkpoints of the POST procedures performed in AMIBIOS were redesigned and supplemented in 1995 and have not undergone significant changes to date. The first description of POST codes or, as AMI calls them, “check points” in their current form appeared in connection with the release of the V6.24 kernel, 07/15/95. Some changes have been made to AMIBIOS V7.0, which are reflected in this document.
Features of performing AMIBIOS startup procedures
If during the startup process the data 55h, AAh appears in the diagnostic port, you should not compare this information with POST codes - we are dealing with a typical test sequence, the task of which is to check the integrity of the data bus.
At the start stage, the output to the diagnostic port of data is specific to each platform. In some implementations, the first code rendered is associated with actions, which AMI calls chipset specific stuff. This procedure is accompanied by outputting the CCh value to port 80h and performing a number of actions to configure the system logic registers. As a rule, the CCh code appears in cases where system logic from Intel is used, built on the basis of the PIIX controller - these are TX, LX, BX chipsets.
Some on-board I/O chips contain an RTC and a keyboard controller, which are disabled at startup. The purpose of the BIOS is to initialize these board resources for further use. In this case, the first start-up procedure associated with setting up the keyboard controller is accompanied by the output of the value 10h, then the RTC is initialized, as evidenced by the appearance of the DDh code in the diagnostic port. It should be noted that the failure of at least one of these resources will result in a non-start of the system board as a whole at the very first stage of POST execution.
On a number of boards, the initialization process begins with the CPU switching to protected mode. In this case, following the first rendered code 43h, the POST execution continues as described in the AMIBIOS documentation - control is transferred to point D0h.
Unpacked initialization procedure codes
Uncompressed Init Code Check Points
Error code | Description of the error |
---|---|
E.E. | In modern AMIBIOS implementations, the first code rendered is associated with accessing the device from which it is possible to boot to restore the BIOS |
CC | Initializing system logic registers CD Flash ROM type not recognized |
C.E. | Checksum mismatch in the starting BIOS CF Error in accessing the spare Flash ROM chip |
DD | Early initialization of the RTC, which is integrated into the SIO chip |
D0 | Disable non-maskable NMI interrupt. Working out the time delay for attenuation of transient processes. Checking the Boot Block checksum, stopping if there is a mismatch |
D1 | Perform memory regeneration procedure and Basic Assurance Test. Switching to 4 GB memory addressing mode |
D3 | Determination of capacity and primary memory test |
D4 | Return to real memory addressing mode. Early initialization of the chip set. Stack Installation |
D5 | Transferring the POST module from Flash ROM to the transit memory area |
D6 | If the checksum does not match or CTRL+Home, a transition to the Flash ROM recovery procedure is performed (Code E0) |
D7 | Transferring control to a utility program that unpacks the system BIOS |
D8 | Complete unpacking of the system BIOS |
D9 | Transferring system BIOS control to Shadow RAM |
D.A. | Reading information from SPD (Serial Presence Detect) DIMM DB modules Setting MTRR of CPU registers |
DC | The memory controller is programmed according to data received from SPD DE System memory configuration error. Fatal error |
DF | System memory configuration error. Beep 10 Early |
11 | Return from STR (Suspend to RAM) state |
12 | Restoring access to SMRAM (System Management RAM) |
13 | Memory regeneration restoration |
14 | Finding and initializing VGA BIOS |
Flash ROM rewrite procedure codes
Boot Block Recovery Codes
Error code | Description of the error |
---|---|
E0 | Preparations are being made to intercept INT19 and the ability to start the system in simplified mode is checked. |
E1 | Setting interrupt vectors |
E3 | Recovering CMOS contents, searching and initializing BIOS |
E2 | Preparing interrupt controllers and direct memory access |
E6 | Enable system timer and FDC interrupts |
E.C. | Reinitializing the IRQ and DMA ED controllers Initializing the disk drive |
E.E. | Reading boot sector from EF floppy Disk operation error |
F0 | Finding the AMIBOOT.ROM file |
F1 | The file AMIBOOT.ROM was not found in the root directory F2 Read FAT |
F3 | Reading AMIBOOT.ROM |
F4 | The size of the AMIBOOT.ROM file does not match the size of the Flash ROM |
F5 | Disabling Internal Cache |
FB | Flash ROM Type Definition |
F.C. | Erasing the main Flash ROM block |
FD | Programming the main Flash ROM block |
FF | Restart BIOS |
Unpacked system BIOS codes executed in ShadowRAM
Runtime code is uncompressed in F000 shadow RAM
Error code | Description of the error |
---|---|
03 | Disable non-maskable NMI interrupt. Reset type definition |
05 | Stack initialization. Disable memory and USB controller caching |
06 | Executing a utility program in RAM |
07 | Processor recognition and APIC initialization |
08 | Checking the CMOS checksum |
09 | Checking the execution of the End/Ins keys |
0A | Battery failure check |
0B | Clearing the keyboard controller buffer registers |
0C | A test command is sent to the keyboard controller |
0E | Finding additional devices supported by the keyboard controller |
0F | Initializing the keyboard |
10 | A reset command is sent to the keyboard |
11 | If the End or Ins key is pressed, the CMOS 12 is reset. Placing the DMA controllers in a passive state. |
13 | Chipset initialization and L2 cache |
14 | Checking the system timer |
19 | DRAM regeneration request generation test is running |
1A | Checking the duration of the regeneration cycle |
20 | Initializing Output Devices |
23 | The keyboard controller input port is read. Keylock Switch and Manufacture Test Switch are interrogated |
24 | Preparing to initialize the interrupt vector table |
25 | Interrupt vector initialization complete |
26 | The status of the Turbo Switch jumper is polled through the keyboard controller input port |
27 | Primary initialization of the USB controller. Updating the microcode of the starting processor |
28 | Preparing to install video mode |
29 | Initializing the LCD panel |
2A | Search for devices supported by additional ROMs |
2B | Initializing VGA BIOS, checking its checksum |
2C | Executing VGA BIOS |
2D | Matching INT 10h and INT 42h |
2E | Search for CGA video adapters |
2F | CGA adapter video memory test |
30 | Test of CGA adapter scan generation circuits |
31 | Error in video memory or scanning circuits. Finding an alternative CGA video adapter |
32 | Test of video memory of an alternative CGA video adapter and scan circuits |
33 | Poll the status of the Mono/Color jumper |
34 | Setting text mode 80x25 |
37 | Video mode is set. Screen cleared |
38 | Initialization of on-board devices |
39 | Displaying error messages from the previous step |
3A | Displaying the “Hit DEL” message to enter CMOS Setup |
3B | Start preparing for a memory test in protected mode |
40 | Preparing GDT and IDT descriptor tables |
42 | Switching to protected mode |
43 | The processor is in protected mode. Interrupts enabled |
44 | Preparing to test the A20 line |
45 | A20 line test |
46 | RAM size determination completed |
47 | Test data recorded in Conventional Memory |
48 | Rechecking Conventional Memory |
49 | Extended Memory Test |
4B | Memory reset |
4C | Indication of the zeroing process |
4D | Recording in CMOS the resulting sizes Conventional and Extended memory 4E Indication of the actual amount of system memory |
4F | Extended Conventional Memory test running |
50 | Conventional Memory size correction |
51 | Extended Memory test |
52 | Conventional Memory and Extended Memory volumes saved |
53 | Delayed parity error handling |
54 | Disable parity and non-maskable interrupt processing |
57 | Initializing the memory region for POST Memory Manager |
58 | You are prompted to enter CMOS Setup |
59 | Returning the processor to real mode |
60 | Checking page DMA registers |
62 | Test of address registers and forwarding length of DMA#1 controller |
63 | Test of address registers and forwarding length of DMA#2 controller |
65 | Programming DMA controllers |
66 | Clearing the Write Request and Mask Set POST registers |
67 | Programming Interrupt Controllers |
7F | Resolving NMI request from additional sources |
80 | Sets the interrupt servicing mode from the PS/2 port |
81 | Keyboard interface test for reset errors |
82 | Setting the keyboard controller operating mode |
83 | Checking Keylock Status |
84 | Memory capacity verification |
85 | Displaying Error Messages |
86 | Configuring the system for Setup operation |
87 | Unpacking the CMOS Setup program into Conventional Memory. |
88 | Setup program completed by user |
89 | Completed state recovery after Setup operation |
8B | Reserving memory for an additional BIOS variable block |
8C | Programming Configuration Registers |
8D | Primary initialization of HDD and FDD controllers |
8F | Reinitializing the FDD Controller |
91 | Configuring the HDD Controller |
95 | Performing a ROM Scan to look for additional BIOSes |
96 | Additional configuration of system resources |
97 | Verifying the signature and checksum of the optional BIOS |
98 | Setting up System Management RAM |
99 | Setting the timer counter and parallel port variables 9A Generating a list of serial ports |
9B | Preparing an area in memory for a coprocessor test |
9C | Initializing the coprocessor |
9D | Coprocessor information is stored in CMOS RAM |
9E | Keyboard Type Identification |
9F | Search for additional input devices |
A0 | Formation of MTRR registers (Memory Type Range Registers) |
A2 | Error messages from previous initialization steps |
A3 | Setting the keyboard auto-repeat timing |
A4 | Defragmenting unused RAM regions |
A5 | Setting the video mode |
A6 | Cleaning the screen |
A7 | Transferring BIOS executable code to Shadow RAM area |
A8 | Initializing additional BIOS in segment E000h |
A9 | Returning control to the system BIOS AA Initializing the USB bus |
AB | Preparing the INT13 module to serve disk services |
A.C. | Building AIOPIC tables to support multiprocessor AD systems Preparing the INT10 module to serve video services |
A.E. | DMI Initialization |
B0 | System Configuration Table Output B1 ACPI BIOS Initialization |
00 | Software interrupt INT19h – Boot Sector loading |
Features of the Device Initialization Manager
In addition to the above POST codes, messages about events during the execution of Device Initialization Manager (DIM) are output to the diagnostic port. There are several control points, which display the initialization status of system or local buses.
The information is displayed in word format, the low byte of which matches the system POST code, and the high byte indicates the type of initialization procedure being performed. The most significant tetrad in the high byte indicates the type of procedure being executed, and the low tetrad determines the bus topology for its application.
Senior tetrad
Junior tetrad
If a system memory configuration error is detected, port 80h is output sequentially in endless loop DE code, DF code, configuration error code, which can take the following values:
2. Award BIOS V4.51PG Elite
AwardBIOS V4.51PG Elite
The dynamically developing company Award Software in 1995 proposed a new solution in the field of low-level software at that time - AwardBIOS "Elite", better known as V4.50PG. The control point maintenance mode has not changed either in the widespread version V4.51 or in the rare version V4.60. The suffixes P and G denote, respectively, support for the PnP mechanism and maintenance of energy saving functions (Green Function).
Performing a POST in Shadow RAM
Error code | Description of the error |
---|---|
03 | Disable NMI, PIE (Periodic Interrupt Enable), AIE (Alarm Interrupt Enable), UIE (Update Interrupt Enable). Prohibition of generation of programmable frequency SQWV |
04 | Checking the generation of requests for DRAM regeneration |
05 | |
06 | Test the memory area starting at address F000h, where BIOS 07 is located Checking the functioning of CMOS and battery power |
BE | Programming the configuration registers of the South and North Bridges |
09 | Initializing the L2 Cache and Advanced Cache Control Registers on the Cyrix Processor |
0A | Generating a table of interrupt vectors. Configuring Power Management Resources and Setting the SMI Vector |
0B | Checking the CMOS checksum. Scanning PCI bus devices. Processor microcode update |
0С | Initializing the Keyboard Controller |
0D | Finding and initializing the video adapter. Setting up IOAPIC. Clock measurements, FSB setting |
0E | MPC initialization. Video memory test. Displaying the Award Logo |
0F | Checking the first DMA 8237 controller. Keyboard detection and its internal test. BIOS checksum verification |
10 | Checking the second DMA 8237 controller |
11 | Checking DMA controller page registers |
14 | Test of system timer channel 2 15 Test of the request masking register of the 1st interrupt controller |
16 | Test of the request masking register of the 2nd interrupt controller 19 Checking the passivity of the NMI non-maskable interrupt request |
30 | Determination of the volume of Base Memory and Extended Memory. APIC setup. Software control of Write Allocation mode |
Error code | Description of the error |
---|---|
31 | The main on-screen RAM test. USB initialization |
32 | The Plug and Play BIOS Extension splash screen appears. Setting up Super I/O resources. Programmable Onboard Audio Device |
39 | Programming the clock generator via the I2C bus |
3C | Setting the software flag to allow entry into Setup |
3D | Initializing PS/2 mouse |
3E | Initializing the External Cache controller and enabling Cache BF Setting up the chipset configuration registers |
41 | Initializing the floppy disk subsystem |
42 | Disable IRQ12 if PS/2 mouse is missing. The hard drive controller is being soft reset. Scanning other IDE devices |
43 | |
45 | Initializing the FPU coprocessor |
4E | Error message display |
4F | Password Request |
50 | Restoring a previously stored CMOS state in RAM |
51 | Resolution of 32 bit access to HDD. Configuring ISA/PnP Resources |
52 | Initializing additional BIOS. Setting the values of PIIX configuration registers. Formation of NMI and SMI |
53 | |
60 | Installation antivirus protection BOOT Sector |
61 | Final steps to initialize the chip set |
62 | Reading keyboard ID. Setting its parameters |
63 | Correction of ESCD, DMI blocks. Clearing RAM |
FF | Transferring control to the bootloader. BIOS executes INT 19h command |
3. Award BIOS V6.0 Medallion
AwardBIOS V6.0 Medallion
The first mention of Award Medallion BIOS, Version 6.0 dates back to May 12, 1999. The structure of the new product remains unchanged, retaining the early (Early), late (Late) and final (System) phases of hardware initialization. Significant changes affected the POST execution algorithms, which was reflected in the new encoding of checkpoints, significantly expanding their scope of application. However, in the new BIOS there was no place for outdated technologies such as EISA, and for this reason a number of POST codes were abolished.
Executing startup POST procedures from ROM
At the early initialization stage, the BIOS program code is executed from the Boot Block in the Flash ROM, and is accompanied by the output of checkpoints 91h...FFh to the diagnostic port
Error code | Description of the error |
---|---|
91 | Selecting a startup script for the CF platform Determining the processor type |
C0 | External Cache prohibition. Internal Cache prohibition. Shadow RAM ban. Programming the DMA controller, interrupt controller, timer, RTC C1 block Determining the memory type, total volume and placement on 0C lines Checking checksums |
C3 | Checking the first 256K DRAM for the Temporary Area organization. Unpacking BIOS in Temporary Area |
C5 | If the checksums match, the POST code being executed is transferred to Shadow. Otherwise, control is transferred to the BIOS recovery procedure |
B0 | Initializing North Bridge |
A0-AF | Hardware-dependent system logic initialization procedure E0-EF Error during system logic initialization process |
BIOS recovery
Performing a POST in Shadow RAM
Late initialization is performed in RAM and continues until the user menu is called - CMOS Setup. This POST phase is characterized by the use of memory segment E000h, in which the passage of checkpoints from 01h to 7Fh is processed.
Error code | Description of the error |
---|---|
01 | Unpacking XGROUP at physical address 1000:0000h |
03 | Early |
05 | Setting the initial values of variables that specify image attributes. Checking the CMOS Status Flag |
07 | Checking and initializing the keyboard controller |
08 | Determining the interface type of the connected keyboard |
0A | Procedure for autodetection of keyboard and mouse. Final settings of the keyboard controller using PCI space registers |
0E | Testing memory segment F000h |
10 | Determining the type of FlashROM installed |
12 | CMOS test |
14 | Chipset register initialization procedure |
16 | Primary initialization of the on-board frequency synthesizer |
18 | Definitions of the installed processor and the size of its Cache L1 and L2 1B Generation of the interrupt vector table |
1C | |
1D | Initial setup of the Power Management system |
1F | Download from external module XGROUP of keyboard matrix |
21 | Initializing the Hardware Power Management subsystem |
23 | Coprocessor testing. Determining the FDD drive type. Preparatory stage for creating a resource map of PnP devices |
24 | Processor microcode update procedure. Resource distribution map update |
25 | Initialization and scanning of the PCI bus |
26 | Configuring the logic that serves the VID (Voltage Identification Device) lines. Initialization of the on-board voltage and temperature monitoring system |
27 | Reinitializing the Keyboard Controller |
29 | Initialization of the APIC included in the central processor. Measuring the frequency at which the processor operates. Setting up system logic registers. Initializing the IDE Controller |
2A | |
2B | Search VGA BIOS |
2D | Displaying processor information |
33 | Performing a Reset on a connected keyboard |
35 | Checking the first channel of the 8237 DMA controller |
37 | Checking the second channel of the DMA 8237 controller |
39 | Testing DMA page registers |
3C | Setting up the Programmable Interval Timer (8254) controller |
3E | Initializing the 8259 Master Controller |
40 | Initialization of Slave controller 8259 |
43 | Preparing the interrupt controller for operation. Interrupts are disabled, they are enabled later, after a memory test |
45 | Checking the Passivity of a Non-Maskable Interrupt (NMI) Request |
47 | Performing ISA/EISA tests |
49 | Determining the amount of basic and extended memory. Software control of Writes Allocation mode by adjusting AMD K5 registers |
4E | Testing memory within the first megabyte and visualizing the results on the display screen. Initializing caching schemes for single and multiprocessor systems, setting up registers on the Cyrix M1 processor |
50 | USB initialization |
52 | Testing of all available system memory, including the region for the built-in video controller (Shared Memory). Visualization of results on the display screen |
53 | Resetting your login password |
55 | Visualization of the number of detected processors |
57 | Initial initialization of ISA PnP devices, each of which is assigned a CSN (Card Select Number). Rendering of the EPA logo |
59 | Initializing the anti-virus support system |
5B | Starting the BIOS update procedure from a 5D floppy drive Initializing on-board SIO and Audio controllers |
60 | Access to CMOS Setup is open |
63 | Initializing PS/2 Mouse |
65 | Initializing USB Mouse |
67 | Use of IRQ12 by PCI devices if there is no PS/2 Mouse in the system 69 Full initialization of the L2 cache controller |
6B | Chipset initialization according to CMOS Setup |
6D | Configuring Resources for ISA PnP Devices in SIO 6F Configuration Mode Initializing the Floppy Disk Subsystem |
73 | Preliminary steps to initialize the hard drive subsystem. On some platforms - poll ALT+F2 to launch AwardFlash |
75 | Finding and initializing IDE devices |
77 | Initializing serial and parallel ports |
7A | Software reset of the coprocessor, writing the control word to the FPU register CW 7C Installing protection against unauthorized writing to hard drives |
7F | Display error messages. Maintaining the DEL and F1 keys |
Preparing tables, arrays and structures for starting the operating system
Starting with code 82h, POST configures the system according to the CMOS settings. Its final phase is executed from the Shadow RAM area (segment E800h) and ends with the transfer of control to the operating system - code FFh.
Error code | Description of the error |
---|---|
82 | Allocates an area in system memory for power management |
83 | Recovering data from a temporary storage stack in CMOS |
84 | Displaying the message “Initializing Plug and Play Cards...” |
85 | USB initialization complete |
86 | Reserved, Carry Flag clearing |
87 | Building SYSID tables in the DMI area |
88 | Reserved, Carry Flag clearing |
89 | Generating ACPI Service Tables |
8A | Reserved, Carry Flag clearing |
8B | Searching and initializing BIOS for additional devices |
8C | Reserved, Carry Flag clearing |
8D | Initializing parity bit maintenance routines |
8E | Reserved, Carry Flag clearing |
8F | IRQ12 resolution for mouse hot plugging 90 Reserved, clear Carry Flag |
91 | Initializing Legacy platform resources |
92 | Reserved, Carry Flag clearing |
93 | Presumably not used |
94 | Final steps to initialize the main set of logic before loading the operating system. The power management system completes initialization. The BIOS startup screen is removed and the resource allocation table is displayed. AMD K6® family processors have specific settings. Firmware Update for Intel Pentium® II Processor Family and Later |
95 | Setting the automatic transition to winter/summer time. Programming the keyboard controller for the auto-repeat frequency |
96 | In multiprocessor systems, final system settings are performed and service tables and fields are created. For processors of the Cyrix family it is carried out additional customization registers Building the ESCD "Extended System Configuration Data" table. Setting the DOS Time counter in accordance with Real Time Clock. Boot device partitions are saved for further use by built-in antivirus tools: Trend AntiVirus or Paragon Anti-Virus Protection. The system speaker emits a POST completion signal. The MSIRQ table is built and saved |
A number of processes occurring in the Award Medallion BIOS are designated by special groups of control points. These include:
System Event codes - control points of system events.
Power Management Debug codes are checkpoints that occur during the execution of APM or ACPI services.
System Error codes - messages about fatal errors.
Debug codes for MP system - initialization points for multiprocessor platforms.
Features of accelerated POST passage
To reduce system boot time, the user can select the "Quick Power On Self Test" option in CMOS Setup. In this case, the completion of POST will be accelerated by refusing to perform some procedures (Quick Boot).
The Quick Boot operating pattern replaces the late and final POST phases and does not affect the operation of the boot block. Award Software offers a codification of the executable expedited POST procedures that differs from the standard one. Quick Boot begins with the output of checkpoint 65h to the diagnostic port and ends with POST code 80h. Control is then transferred to the operating system, displaying the usual Award BIOS code FFh.
Error code | Description of the error |
---|---|
65 | Early initialization of the SIO controller, software reset of the video controller. Setting up the keyboard controller, testing the keyboard and mouse. Initializing the sound controller. Checking the integrity of BIOS structures. Unpacking Flash ROM maintenance procedures. Initializing the onboard frequency synthesizer |
66 | Initializes the L1/L2 cache according to the results obtained from the CPUID command. Generation of a vector table consisting of pointers to interrupt handling routines. Initializing Power Management Hardware |
67 | Checking CMOS and battery power plausibility. Configuring chipset registers according to CMOS settings. Initializing the keyboard controller as part of the chipset. Formation of BIOS Data Area Variables |
68 | Initializing the video system |
69 | Configuring i8259 interrupt controller |
6A | An accelerated single-pass RAM test is performed using a special algorithm |
6B | Visualization of the number of detected processors, the EPA logo and a prompt to launch the AwardFlash utility. Configuring embedded I/O controller resources in configuration mode |
70 | Invitations to enter Setup. Initializing PS/2 and USB Mouse |
71 | Initializing the cache controller |
72 | Setting up system logic configuration registers. Generating a list of Plug and Play devices. Initializing the FDD controller |
73 | Initializing the HDD controller |
74 | Initializing the coprocessor |
75 | If specified by the user in CMOS Setup, the IDE HDD is write protected. |
77 | Request for a password and display the message: “Press F1 to continue, DEL to enter Setup” |
78 | Initializing BIOS for additional devices on ISA and PCI buses |
79 | Initializing Legacy platform resources |
7A | Generating the root table RSDT and device tables DSDT, FADT, etc. |
7D | Finding information about boot device partitions |
7E | Configuring BIOS services before booting the operating system |
7F | Setting the NumLock flag according to CMOS SetUp |
80 | Transferring control to the operating system |
Performing a POST in Power Saving Mode
One of the platform states, when the contents of RAM are stored on the hard disk, is called Hibernate. In the ACPI specification ("Advanced Configuration and Power Interface Specification", Revision 2.0a dated 03/31/2002) it is defined as the S4 (Non-Volatile Sleep) power saving mode. Returning to full function requires a special way of completing POST.
The ACPI S4 operating scheme, as with the accelerated start, replaces the late and final POST phases. An essential point is checking the startup script in the boot block. Depending on what ACPI state the system is in after the hardware Reset signal, a decision is made to exit state S4, which begins with the output of test point 90h to the diagnostic port and ends with POST code 9Fh.
Error code | Description of the error |
---|---|
90 | Early initialization of the SIO controller, software reset of the video controller. Setting up the keyboard controller, testing the keyboard and mouse |
91 | CMOS and Battery Validation Check |
92 | Initialization of system logic registers and on-board frequency synthesizer |
93 | Initializing the cache using CPUID information |
94 | Generation of a vector table consisting of pointers to interrupt handling routines. Initializing Power Management Hardware |
95 | PCI bus scanning |
96 | Initializing the embedded keyboard controller |
97 | Initializing the video system |
98 | VGA adapter message output |
99 | Checking the first channel of the DMA8237 controller by writing and control reading the base address and forwarding block length registers 9A Configuring the i8259 interrupt controller |
9B | Initializing PS/2 and USB Mouse. Unpacking ACPI code. Initializing the cache controller |
9C | Setting up system logic configuration registers. Generating a list of Plug and Play devices. Initialization of FDD and HDD controllers |
9D | The PM region is not reserved in system memory if it is created in Shadow RAM or SMRAM. In some cases, a repeated, final initialization of the USB bus is required, performed with the L1 cache disabled |
9E | Setting up Power Management, which is part of the system logic. Initialization of SMI generation circuits and installation of the SMI vector. Programming resources responsible for monitoring PM system events |
9F | The disable and enable operation clears the L1/L2 cache and restores its current size. The power saving mode control settings specified in CMOS Setup are saved in PM RAM. For mobile platforms, a check is made to return to full operation after turning off all supply voltages (Zero Volt Suspend mode) |
4. Phoenix BIOS 4.0 Release 6.0
Phoenix Technologies, Ltd.
One of the leaders in low-level software development, Phoenix Technologies, has released a new version of PhoenixBIOS 4.0 to coincide with the release of Windows95. Support for the Intel Pentium processor family is reflected in the names of the intermediate revisions. One of the latest - Release 6.0 - formed the basis for all released BIOS. With the advent of Release 6.1, there were no significant changes in the execution of POST procedures, and, therefore, this did not affect the indication of checkpoints.
A distinctive feature of PhoenixBIOS is that if during the POST execution errors occur when testing 512 KB of main memory (codes 2Ch, 2Eh, 30h), additional information is output to port 80h in word format, the bits of which identify the failed address line or data cell. For example, the code "2C 0002" means that a memory fault has been detected on address line 1. The code "2E 1020" in this case will mean that a fault has been detected on data lines 12 and 5 in the low byte of the memory data bus. On 386SX systems that use a sixteen-bit data bus, an error cannot occur during code execution step 30h
The POST code output to the diagnostic port is accompanied by an audio signal output to the system speaker. The sound signal generation scheme is as follows:
- The eight-bit code is converted into four two-bit groups
- The value of each group increases by one
- Based on the received value, a short sound signal is generated (for example: code 16h = 00 01 01 10 = 1-2-2-3)
Executing startup POST procedures from ROM
Error code | Description of the error |
---|---|
01 | Initializing the Baseboard Management Controller (BMC) |
02 | Checking the current processor operating mode |
03 | Disabling non-maskable interrupts |
04 | The type of installed processor is determined |
06 | Initial settings of the PIC and DMA registers |
07 | The memory area designated for the BIOS copy is reset to zero |
08 | Early initialization of system logic registers |
09 | Setting the POST software flag |
0A | Initializing processor software resources |
0B | Internal Cache permission |
0E | Initializing Super I/O Resources |
0C | Initialize L1/L2 cache according to CMOS values |
0F | Initializing the IDE |
10 | Initializing the Power Management subsystem |
11 | Setting Alternate Register Values |
12 | The value of the MSW (Machine Status Word) register is being set. |
13 | Early provisioning of PCI devices |
14 | Initializing the Keyboard Controller |
16 | Checking the ROM BIOS checksum |
17 | Determining L1/L2 cache size |
18 | Initializing the 8254 system timer |
1A | Initializing the DMA Controller |
1C | Resetting programmable interrupt controller values |
20 | Checking the generation of DRAM regeneration requests |
22 | Checking the operation of the keyboard controller |
24 | Installing a selector for servicing a flat 4Gb memory model |
26 | A20 line resolution |
28 | Determining the total amount of installed memory |
29 | Initializing POST Memory Manager (PMM) |
2A | Resetting 640Kb of main memory |
2C | Testing address lines |
2E | Failure on one of the data lines in the low byte of the memory data bus |
2F | Selecting a cache memory protocol |
30 | Available system memory test |
32 | Determining CPU clock parameters and bus frequency |
Error code | Description of the error |
---|---|
33 | Initializing Phoenix Dispatch Manager |
34 | Prohibiting Power Off Using ATX Power Button |
35 | Settings of system logic registers that control the formation of timing characteristics of access to memory, input/output ports, system and local buses |
36 | A restart is performed if the transition to the next POST procedure fails. The sequence of procedures is managed by Watch Dog Service |
37 | The process of setting up system logic registers is completed. |
38 | The contents of the BIOS Runtime module are unpacked and rewritten into the area intended for Shadow RAM |
39 | Reinitializing the Cache Controller |
3A | L2 cache resize |
3B | Initializing BIOS Execution Trace |
3C | Additional configuration of logic registers to configure PCI-PCI bridges and support for distributed PCI buses |
3D | The system logic registers are configured in accordance with the CMOS Setup settings |
3E | Read Hardware Configuration |
3E | Checking the ROM Pilot system connection |
40 | Determining CPU clock parameters |
41 | Initializing ROM Pilot - remote boot control |
42 | |
44 | Set BIOS Interrupt |
45 | Initializing devices before enabling the PnP mechanism |
46 | The BIOS checksum is calculated using a special algorithm |
47 | Initializing I2O I/O controllers |
48 | Search for video adapter |
49 | PCI Initialization |
4A | Initializing system video adapters |
4B | Quiet Boot is running - a shortened system startup sequence used to speed up POST. |
4C | VGA BIOS contents are rewritten to the transit area |
4E | Visualization of BIOS text string Copyright |
4F | Reserving memory for the boot device selection menu |
50 | The processor type and its clock frequency are visualized |
51 | Initializing the EISA controller and devices |
52 | Keyboard Controller Programming |
54 | Keyboard sound mode activated |
55 | |
58 | Finding unserviced interrupt requests |
59 | Initializing the POST Display Service (PDS) procedure 5A Displaying the message “Press F2 to enter SETUP” |
5B | Disable CPU Internal Cache |
5C | Conventional Memory Check |
5E | Detect Base Address |
60 | Extended Memory Check |
62 | Checking Extended Memory Address Lines |
64 | Transferring control to an executable block generated by the motherboard manufacturer (Patch1) |
66 | Configuring cache control registers |
67 | Minimal initialization of APIC controllers |
68 | L1/L2 cache resolution |
69 | Preparing System Management Mode RAM |
6A | External Cache volume is visualized |
6B | Setting CMOS Setup Defaults |
6C | Visualization of Shadow RAM usage information |
6E | Visualization of information about Upper Memory Blocks (UMB) |
70 | Displaying Error Messages |
72 | Checking the current system configuration and CMOS information |
76 | Checking Keyboard Error Information |
7A | Checking the status of the software (System Password) or hardware (Key Lock Switch) keyboard lock |
7C | Setting hardware interrupt vectors |
7D | Initializing the power tracking system |
7E | Initializing the coprocessor |
80 | On-board SIO I/O controller is prohibited |
81 | Preparing to boot the operating system |
82 | Finding and identifying RS232 ports |
83 | Configuring external IDE controllers |
84 | Finding and identifying parallel ports |
85 | Initializing ISA PnP Devices |
86 | On-board resources of the SIO controller are configured in accordance with the CMOS Setup settings |
87 | Configuring MCD (Motherboard Configurable Devices) |
88 | The values of the variable block in the BIOS Data Area are set |
89 | Allows generation of a non-maskable interrupt |
8A | Setting the values of variables located in the Extended BIOS Data Area |
8B | Checking PS/2 Mouse connection diagrams |
8C | Initializing the drive controller |
8F | Determining the number of connected ATA devices |
90 | Initializing and configuring hard drive controllers |
91 | Setting timing parameters work hard drives in PIO mode |
92 | Transferring control to an executable block generated by the motherboard manufacturer (Patch2) |
93 | Building a multiprocessor system configuration table |
95 | Selecting CD-ROM Maintenance Procedure |
96 | Return to Real Mode |
97 | Building MP Configuration Table |
98 | ROM Scan in progress |
99 | Checking the status of the SMART parameter 9A The contents of the ROM are written to RAM |
9C | Setting up the Power Management subsystem |
9D | Initializing resources to protect against unauthorized access |
9E | Hardware interrupts are enabled |
9F | The number of IDE and SCSI drives is determined |
A0 | Setting DOS Time based on RTC state A1 The purpose of this code is unknown A2 Checking the Key Lock state |
A4 | Keyboard Auto-Repeat Characteristics Settings |
A8 | The "Press F2 to enter Setup" message is removed from the screen |
A.A. | The presence of the SCAN code of the F2 key in the input buffer AC is checked. The Setup program is launched. |
A.E. | The restart flag executed by CTRL+ALT+DEL B0 is cleared. The message "Press F1 to resume, F2 to Setup" is generated. |
B1 | POST progress flag is cleared B2 POST completed |
B4 | Sound signal before booting |
B5 | Quiet Boot phase completed |
B6 | Password check if this mode is enabled in Setup B7 Initializing ACPI BIOS |
B9 | Searching for boot devices on the USB bus BA Initializing DMI parameters |
BB | Repeating the ROM Scan procedure |
B.C. | The RAM parity error latching trigger is reset. |
BD | A menu is displayed for selecting a boot device BE Clearing the screen before loading the operating system BF Activating anti-virus support |
C0 | The software interrupt processing procedure INT 19h is launched - the Boot Sector loader. The interrupt service routine sequentially attempts to load the Boot Sector by polling disk devices in the order prescribed by Setup |
C1 | Initialization of fault maintenance routine (PEM) C2 Calling service routines for error logging |
C3 | Visualization of error messages in the order they were received C4 Setting initial state flags |
C5 | Initializing an extended block of CMOS RAM cells |
C6 | Initial initialization of the docking station |
C7 | Lazy dock initialization |
C8 | Execution of test procedures included in the Boot Block to determine the integrity of BIOS structures |
C9 | Checking the integrity of structures and/or modules external to the system BIOS |
C.A. | Running Console Redirect to serve a remote CB keyboard Emulate disk devices in RAM/ROM |
CC | Run Console Redirect to serve video CDs Support PCMCIA communications |
C.E. | Setting up the Light Pen Controller |
Fatal Error Messages
D0 Error caused by an exceptional situation (Exception error) D2 Calling an interrupt handling procedure from an unidentified source D4 Error associated with a violation of the protocol for issuing and clearing interrupt requests D6 Exiting protected mode with software reset generation D7 To save the state of the video adapter, more is required amount of memory than is available in SMRAM D8 Error during software generation of the processor reset pulse DA Loss of control when returning to Real Mode DC Exit from protected mode with software reset generation without re-initializing the interrupt controller DD Error when testing extended memory DE Keyboard controller error DF Line control error A20 19
Executing Procedures from Boot Block
Error code | Description of the error |
---|---|
E0 | Setting up E1 chipset configuration registers Initializing the North and South Bridges |
E2 | Initializing the CPU |
E3 | Initializing the system timer |
E4 | Initializing Super I/O Resources |
E5 | Checking the status of Recovery Jumper, the installation of which forces the BIOS Recovery mode to start |
E6 | BIOS checksum verification |
E7 | Control is transferred to the BIOS if its checksum is calculated correctly E8 Initialize MPS support |
E9 | Transition to a flat 4Gb memory model |
E.A. | Initialization of non-standard equipment |
E.B. | Configuring the interrupt controller and direct memory access |
E.C. | By writing and control readings using a special algorithm, the memory type is determined: FPM, EDO, SDRAM, and the Host Bridge configuration registers are adjusted in accordance with the result |
ED | By means of records and control readings using a special algorithm, the volume of memory banks and placement in rows are determined. In accordance with the result, the Host Bridge configuration registers (DRAM Row Boundary) are configured |
E.E. | The contents of the Boot Block are copied to Shadow RAM EF Preparing SMM RAM for the SMI handler |
F0 | Memory test |
F1 | Initializing interrupt vectors |
F2 | Initializing Real Time Clock |
F3 | Initializing the video subsystem |
F4 | Generating a beep before booting |
F5 | Loading the operating system stored in Flash ROM |
F6 | Return to Real Mode |
F7 | Boot to Full DOS |
F8 | Initializing the USB controller |
FA…FF | Codes for interaction with the PhDebug procedure |
5. Insyde BIOS Mobile Pro
Insyde Software Corp.
The mobile systems market insider has firmly established itself in areas where loyalty to tradition and a conservative approach to BIOS design is required. Having inherited source code from SystemSoft, the company is constantly working to improve it. The latest revision of MobilePRO is actively used in Mitac and Clevo laptops, the documentation for which formed the basis of the Error Codes table - this is what Insyde Software calls POST checkpoints.
Boot block checkpoints
Despite the fact that Insyde Software created its first BIOS in 1992, the established model of the boot block - or Boot Loader, as the creators themselves called it - was finally formed only by the end of 1995. From this moment on, the starting procedure was numbered by version and creation date.
The most significant point from the point of view of a service engineer examining the process of booting a computer system with InsydeBIOS is the diagnostic code display device. Although, as a rule, Boot Loader uses Manufacture's Diagnostic Port 80h, standard in such cases, in some cases, test point output is performed only on the PIO Port (Parallel Input/Output port for diagnostic purpose), which is nothing more than a parallel port 378h There are implementations in which diagnostic codes sent to port 80h are duplicated to the parallel port.
Error code | Description of the error |
---|---|
00 | Starting point for boot block execution 01 Inhibit line A20 (not used) |
02 | CPU microcode update |
03 | Testing RAM |
04 | Transferring the boot block to RAM |
05 | Executing a boot block from RAM |
06 | Forcing the Flash ROM recovery procedure |
07 | Transferring the system BIOS to RAM |
08 | System BIOS checksum verification |
09 | Running the POST procedure |
0A | Starting the Flash ROM recovery procedure from an FDD drive |
0B | Initializing the frequency synthesizer |
0C | Completing the BIOS recovery procedure |
0D | Alternative procedure for recovering Flash ROM from FDD |
0F | Stopping if a fatal error occurs |
BB | LPC SIO early initialization |
CC | Starting point for starting Flash ROM recovery |
88 | Enabling ACPI Features |
99 | Error when exiting STR mode |
60 | Switching to Big Real Mode |
61 | Initialization of SM Bus. SPD data is stored in CMOS A0 Read and parse SPD fields previously stored in CMOS A1 Memory controller initialization |
A2 | Defining Logical Banks DIMM module |
A3 | Programming DRB registers (DRAM Row Boundary) |
A4 | Programming DRA Registers (DRAM Row Attributes) |
A.E. | DIMMs have been detected in the system that differ in their Error Correcting Codes (ECC) functions. |
A.F. | Primary initialization of memory controller registers mapped to memory space |
E1 | The boot procedure fails if the DIMM is not equipped with an SPD chip |
E2 | DIMM type does not match system requirements |
E.A. | The minimum time between activating DIMM strings and entering the regeneration state does not meet system requirements |
E.C. | Register modules are not supported ED Checking CAS Latency modes |
E.E. | DIMM organization not supported by motherboard |
Executing POSTs from RAM
The most modern InsydeBIOS solutions use 16-bit checkpoint mapping. This is done using ports 80h and 81h, the latter of which is intended to extend standard diagnostics.
The study of control points is made difficult by their irregular construction, when processes of different meaning are accompanied by the same codes. In dual diagnostic systems, there are differences of a different order: some POST codes are displayed only in one of the ports without the usual duplication in such cases.
Error code | Description of the error |
---|---|
10 | Cache initialization, CMOS check |
11 | Line A20 prohibited. Setting registers for 8259 controllers. |
12 | Determining the boot method |
13 | Initializing the Memory Controller |
14 | Searching for a video adapter connected to the ISA bus |
15 | Setting System Timer Values |
16 | Setting system logic registers using CMOS |
17 | Calculating the total amount of RAM |
18 | Testing the low page of Conventional Memory |
19 | Verifying the checksum of the Flash ROM image |
1A | Resetting the Interrupt Controller Registers |
1B | Initializing the video adapter |
1C | Initializing a subset of video adapter registers compatible with program model 6845 |
1D | Initializing the EGA adapter |
1E | Initializing the CGA adapter |
1F | DMA controller page register test |
20 | Checking the keyboard controller |
21 | Initializing the Keyboard Controller |
22 | Comparison of the resulting amount of RAM with the value in CMOS |
23 | Checking battery backup and Extended CMOS |
24 | Testing DMA Controller Registers |
25 | Setting DMA controller parameters |
26 | Formation of the interrupt vector table |
27 | Accelerated determination of the amount of installed memory |
28 | Protected Mode |
29 | System memory test completed |
2A | Exiting Protected Mode |
2B | Transferring the Setup procedure to RAM |
2C | Starting the video initialization procedure |
2D | Re-search for CGA adapter |
2E | Re-search for EGA/VGA adapter |
2F | Displaying VGA BIOS messages |
30 | Custom Keyboard Controller Initialization Routine |
31 | Checking the connected keyboard |
32 | Checking the passage of a request from the keyboard |
33 | Checking the Keyboard Status Register |
34 | Test and reset system memory |
35 | Protected Mode |
36 | Extended memory test completed |
37 | Exiting Protected Mode |
38 | A20 line ban |
39 | Initializing Cache Controller 3A Checking the System Timer |
3B | Setting the DOS Time counter according to Real Time Clock |
3C | Initializing the hardware interrupt table |
3D | Finding and initializing manipulators and pointers |
3E | Setting the status of the NumLock key |
3F | Initializing serial and parallel ports |
40 | Configuring Serial and Parallel Ports |
41 | Initializing the FDD controller |
42 | Initializing the HDD controller |
43 | Initializing Power Management for the USB Bus |
44 | Finding and initializing additional BIOS |
45 | Resetting the NumLock key status |
46 | Checking coprocessor functionality |
47 | Initializing PCMCIA |
48 | Preparing to start the operating system |
49 | Transferring control to executable Bootstrap code |
50 | ACPI initialization |
51 | Initializing Power Management |
52 | Initializing the USB Bus Controller |
Description: I bring to your attention the main POST codes forBIOSmanufacturerAMI. A short introduction. Immediately after pressing the POWER button on the system unit of the personal computer, control of the PC goes directly to the BIOS. At this time (at the beginning of the PC startup), the processor sends a signal to the BIOS chip, which initializes the loading of the BOOT-ROUTINE firmware of the Basic I/O System. Subroutine POST (Power-On Self Test) tests the equipment installed on the computer, configures it and prepares it for work. A separate test is performed for each individual piece of equipment (processor, memory, video card, keyboard, input/output ports, etc.). Each test has its own unique number, which is called a POST code. POST code written to the Manufacturing Test Port (with address 0080H) before running each individual POST test. After the POST test code is written to the Manufacturing Test Port, the testing procedure for the corresponding equipment begins. If the testing procedure fails, the POST code of the last procedure (which caused the error) remains in the Manufacturing Test Port. If you know the POST code of the last procedure, you can determine the device that caused the error. Reading POST codes can be done in several ways. Since BIOS is produced by several manufacturers, each BIOS from an individual manufacturer has its own table of POST codes.
The BOOT-ROUTINE firmware calls the POST self-test routine.
This table contains POST codes that are displayed during the full POST procedure.
- CF Detects processor type and tests CMOS read/write
- C0 The chipset and L1-, L2-cache are pre-initialized, the interrupt controller, DMA, timer are programmed
- C1 The type and amount of RAM is detected
- C3 BIOS code is unpacked into a temporary area of RAM
- 0C BIOS checksums are checked
- C5 BIOS code is copied to shadow memory and control is transferred to the Boot Block module
- 01 XGROUP module is unpacked at physical address 1000:0000h
- 02 Processor initialization. The CR and MSR registers are set
- 03 I/O resources are determined (Super I/O)
- 05 Clears screen and CMOS status flag
- 06 Coprocessor is being checked
- 07 Keyboard controller is identified and tested
- 08 Keyboard interface is detected
- 09 Initializing the Serial ATA controller
- OA Detects the keyboard and mouse that are connected to the PS/2 ports
- 0B AC97 audio controller resources are being installed
- OE Testing memory segment F000h
- 10 The type of flash memory is determined
- 12 CMOS tested
- 14 Sets values for chipset registers
- 16 The clock generator is initially initialized
- 18 The type of processor, its parameters and L1 and L2 cache sizes are determined
- 1B The interrupt vector table is initialized
- 1C Checks CMOS checksums and battery voltage
- 1D Power management system is defined
- 1F Loads the keyboard matrix (for laptops)
- 21 The Hardware Power Management system is initializing (for laptops)
- 23 Math coprocessor, disk drive, chipset initialization are tested
- 24 The processor microcode is being updated. Creates a resource distribution map for Plug and Play devices
- 25 Initial PCI initialization: lists devices, searches for VGA adapter, writes VGA BIOS to C000:0
- 26 The clock frequency is set according to CMOS Setup. Synchronization of unused DIMM and PCI slots is disabled. The monitoring system (H/W Monitor) is initialized
- 27 Interrupt INT 09h enabled. The keyboard controller is initialized again
- 29 MTRR registers are programmed, APIC is initialized. The IDE controller is being programmed. The processor frequency is measured. The video system BIOS extension is called
- 2B Search for video adapter BIOS
- 2D The Award splash screen is displayed, information about the processor type and its speed
- 33 Keyboard reset
- 35 First DMA channel being tested
- 37 Second DMA channel being tested
- 39 DMA page registers are tested
- 3C Configuring 8254 controller (timer)
- 3E Checking the 8259 interrupt controller
- 43 Interrupt controller is checked
- 47 ISA/EISA buses are tested
- 49 The amount of RAM is calculated. Registers are being configured for the AMD K5 processor
- 4E MTRR registers are programmed for Syrix processors. L2 cache and APIC are initialized
- 50 USB bus detected
- 52 The RAM is tested and the results are displayed. Clearing extended memory
- 53 If the CMOS is cleared, the login password is reset
- 55 Displays the number of processors (for multiprocessor platforms)
- 57 The EPA logo is displayed. Initial Initialization of ISA PnP Devices
- 59 Virus protection system is determined
- 5B Prompt for running BIOS update from floppy disk
- 5D Launches Super I/O controller and integrated audio controller
- 60 Entering CMOS Setup if the Delete key was pressed
- 65 PS/2 mouse is initializing
- 69 L2 cache enabled
- 6B Chipset registers are configured according to BIOS Setup
- 6D Assigns resources for ISA PnP devices and COM ports for integrated devices
- 6F Initializes and configures the floppy disk controller
- 75 IDE devices are detected and installed: hard drives, CD/DVD, LS-120, ZIP, etc.
- 76 Information about detected IDE devices is displayed
- 77 Serial and parallel ports are initialized
- 7A The math coprocessor is reset and ready for operation.
- 7C Defines protection against unauthorized writing to hard drives
- 7F If there are errors, a message is displayed and the Delete and F1 keys are pressed
- 82 Memory is allocated for power management and changes are written to the ESCD table.
- The splash screen with the EPA logo is removed. Requests a password if needed
- 83 All data is saved from the temporary stack to CMOS
- 84 Displaying Initializing Plug and Play Cards message
- 85 USB initialization complete
- 87 SYSID tables are created in the DMI area
- 89 ACPI tables are being installed. Interrupts are assigned to PCI devices
- 8B Called by the BIOS of additional ISA or PCI controllers, with the exception of the video adapter
- 8D Sets RAM parity parameters using CMOS Setup. APM is initialized
- 8F IRQ 12 is allowed for hot plugging of a PS/2 mouse
- 94 Completion of chipset initialization. Displays the resource allocation table. Enable L2 cache. Setting the summer/winter time transition mode
- 95 Sets the keyboard auto-repeat frequency and Num Lock state
- 96 For multiprocessor systems, registers are configured (for Cyrix processors). The ESCD table is created. The DOS Time timer is set according to the RTC CMOS clock. Boot device partitions are saved for use by the built-in antivirus. The speaker announces the end of POST. The MSIRQ FF table is created. The BIOS interrupt INT 19h is executed. Search for the bootloader in the first sector of the boot device
A shortened procedure is performed by setting the Quick Power On Self Test option in the BIOS.
- 65 The video adapter is being reset. The sound controller and input/output devices are initialized, the keyboard and mouse are tested. BIOS integrity is checked
- 66 Cache is initializing. An interrupt vector table is created. The power management system is initializing
- 67 The CMOS checksum is checked and the battery is tested. Chipset is configured based on CMOS parameters
- 68 Video adapter is initializing
- 69 Configuring the interrupt controller
- 6A Testing RAM (accelerated)
- 6B Displays EPA logo, CPU and memory test results
- 70 A prompt to enter BIOS Setup is displayed. A mouse connected to PS/2 or USB is initialized
- 71 Cache controller is initializing
- 72 Chipset registers are being configured. A list of Plug and Play devices is created.& The drive controller is initialized
- 73 Hard disk controller is initializing
- 74 Coprocessor is initializing
- 75 If necessary, the hard drive is write-protected
- 77 If necessary, a password is requested and messages Press F1 to continue, DEL to enter Setup are displayed
- 78 Expansion cards with their own BIOS are initialized
- 79 Platform resources are initializing
- 7A The root table RSDT, device tables DSDT, FADT, etc. are generated.
- 7D Collects information about boot device partitions
- 7E BIOS is preparing to boot the operating system
- 7F The NumLock indicator status is set according to the settings
- BIOS Setup
- 80 INT 19 is called and the operating system starts
AMIBIOS8.0
- D0 Initialization of the processor and chipset. Checking BIOS boot block checksums
- D1 Initialization of I/O ports. The command for the BAT self-test is sent to the keyboard controller
- D2 Disable L1/L2 cache. The amount of installed RAM is determined
- D3 Memory regeneration schemes are configured. Allowed to use cache memory
- D4 Test 512 KB memory. The stack is installed and the communication protocol with the cache memory is assigned
- D5 BIOS code is unpacked and copied to shadow memory
- D6 Checks BIOS checksums and pressing Ctrl+Home keys (BIOS recovery)
- D7 Control is transferred to the interface module, which unpacks the code into the Run-Time area
- D8 The executable code is unpacked from flash memory into operational memory. CPUID information is saved
- D9 The unpacked code is transferred from the temporary storage area to segments 0E000h and 0F000h of RAM
- DA CPUID registers are restored. POST execution is moved to RAM
- E1–E8, EC–EE Errors related to the system memory configuration
- 03 Processing of NMI, parity errors, and output of signals to the monitor is prohibited. An area is reserved for the GPNV event log, the initial values of variables from the BIOS are set
- 04 Checks battery health and calculates CMOS checksum
- 05 The interrupt controller is initialized and the vector table is built
- 06 The timer is being tested and prepared for operation
- 08 Keyboard testing (keyboard lights flashing)
- C0 Initial processor initialization. Do not use cache memory. Defined by APIC
- C1 For multiprocessor systems, the processor responsible for starting the system is determined
- C2 Completes the assignment of the processor to start the system. Identification using CPUID
- C5 The number of processors is determined and their parameters are configured
- C6 Initializes cache memory for faster POST.
- C7 Processor initialization completes
- 0A Keyboard controller detected
- 0B Search for a mouse connected to the PS/2 port
- 0C Checking for keyboard presence
- 0E Various input devices are detected and initialized
- 13 Initial initialization of chipset registers
- 24 Platform-specific BIOS modules are unpacked and initialized.
- An interrupt vector table is created and interrupt processing is initialized
- 2A The DIM mechanism identifies devices on local buses. The video adapter is being prepared for initialization, a resource distribution table is being built
- 2C Detection and initialization of the video adapter, the video adapter is called by the BIOS
- 2E Finding and initializing additional I/O devices
- 30 Prepares for SMI processing
- 31 ADM module is initialized and activated
- 33 The simplified loading module is initializing
- 37 AMI logo, BIOS version, processor version, key prompt to enter BIOS is displayed
- 38 Using DIM, various devices on local buses are initialized
- 39 DMA controller is initializing
- 3A Sets the system time according to the RTC clock
- 3B RAM is tested and results are displayed
- 3C Chipset registers are configured
- 40 Serial and parallel ports, mathematical coprocessor, etc. are initialized.
- 52 Based on the results of the memory test, the RAM data in CMOS is updated
- 60 BIOS Setup sets the NumLock state and configures auto-repeat parameters
- 75 The procedure for working with disk devices is started (interrupt INT 13h)
- 78 A list of IPL devices is created (from which the operating system can be loaded)
- 7C ESCD extended system configuration tables are created and written to NVRAM
- 84 Log errors encountered during POST
- 85 Messages are displayed about detected non-critical errors.
- 87 If necessary, BIOS Setup is launched, which is first unpacked into RAM
- 8C Chipset registers are configured in accordance with BIOS Setup
- 8D ACPI tables are built
- 8E Configures non-maskable interrupt (NMI) service
- 90 SMI is finally initialized
- A1 Clearing data that is not needed when loading the operating system
- A2 EFI modules are prepared to interact with the operating system
- A4 In accordance with the BIOS Setup language module is initialized
- A7 The POST procedure summary table is displayed
- A8 Sets the state of the MTRR registers
- A9 If necessary, waits for keyboard commands to be entered
- AA Removes POST interrupt vectors (INT 1Ch and INT 09h)
- AB Devices for loading the operating system are detected
- AC The final stages of setting up the chipset in accordance with BIOS Setup
- B1 ACPI interface is configured
- 00 Interrupt processing INT 19h is called (boot sector search, OS loading)
Phoenix Bios 4.0
- 02 Verify Real Mode
- 03 Disable Non-Maskable Interrupt (NMI)
- 04 Get CPU type
- 06 Initialize system hardware
- 08 Initialize chipset with initial POST values
- 09 Set IN POST flag
- 0A Initialize CPU registers
- 0B Enable CPU cache
- 0C Initialize caches to initial POST values
- 0E Initialize I/O component
- 0F Initialize the local bus IDE
- 10 Initialize Power Management
- 11 Load alternate registers with initial POST values
- 12 Restore CPU control word during warm boot
- 13 Initialize PCI Bus Mastering devices
- 14 Initialize keyboard controller
- 16 (1-2-2-3) BIOS ROM checksum
- 17 Initialize cache before memory autosize
- 18 8254 timer initialization
- 1A 8237 DMA controller initialization
- 1C Reset Programmable Interrupt Controller
- 20 (1-3-1-1) Test DRAM refresh
- 22 (1-3-1-3) Test 8742 Keyboard Controller
- 24 Set ES segment register to 4 GB
- 26 Enable A20 line
- 28 Autosize DRAM
- 29 Initialize POST Memory Manager
- 2A Clear 512 KB base RAM
- 2C (1-3-4-1) RAM failure on address line xxxx
- 2E (1-3-4-3) RAM failure on data bits xxxx of low byte of memory bus
- 2F Enable cache before system BIOS shadow
- 30 (1-4-1-1) RAM failure on data bits xxxx of high byte of memory bus
- 32 Test CPU bus-clock frequency
- 33 Initialize Phoenix Dispatch Manager
- 34 Disable Power Button during POST
- 35 Re-initialize registers
- 36 Warm start shut down
- 37 Re-initialize chipset
- 38 Shadow system BIOS ROM
- 39 Re-initialize cache
- 3A Autosize cache
- 3C Advanced configuration of chipset registers
- 3D Load alternate registers with CMOS values
- 40 CPU speed detection
- 42 Initialize interrupt vectors
- 45 POST device initialization
- 46 (2-1-2-3) Check ROM copyright notice
- 48 Check video configuration against CMOS
- 49 Initialize PCI bus and devices
- 4A Initialize all video adapters in system
- 4B QuietBoot start (optional)
- 4C Shadow video BIOS ROM
- 4E Display BIOS copyright notice
- 50 Display CPU type and speed
- 51 Initialize EISA board
- 52 Test keyboard The keyboard is being tested
- 54 Set key click if enabled
- 55 Initialize USB bus
- 58 (2-2-3-1) Test for unexpected interrupts
- 59 Initialize POST display service
- 5A Display prompt “Press F2 to enter SETUP”
- 5B Disable CPU cache
- 5C Test RAM between 512 and 640 KB
- 60 Test extended memory
- 62 Test extended memory address lines
- 64 Jump to UserPatch1
- 66 Configure advanced cache registers
- 67 Initialize Multi Processor APIC
- 68 Enable external and CPU caches
- 69 Setup System Management Mode (SMM) area
- 6A Display external L2 cache size
- 6B Load custom defaults (optional)
- 6C Display shadow-area message
- 6E Display possible high address for UMB recovery
- 70 Display error messages Error messages are displayed
- 72 Check for configuration errors
- 76 Check for keyboard errors
- 7C Set up hardware interrupt vectors
- 7D Initialize hardware monitoring
- 7E Initialize coprocessor if present
- 80 Disable onboard Super I/O ports and IRQs
- 81 Late POST device initialization
- 82 Detect and install external RS232 ports
- 83 Configure non-MCD IDE controllers
- 84 Detect and install external parallel ports
- 85 Initialize PC-compatible PnP ISA devices
- 86 Re-initialize onboard I/O ports
- 87 Configure Motheboard Configurable Devices (optional)
- 88 Initialize BIOS Data Area
- 89 Enable Non-Maskable Interrupts (NMIs)
- 8A Initialize Extended BIOS Data Area
- 8B Test and initialize PS/2 mouse
- 8C Initialize floppy controller
- 8F Determine number of ATA drives (optional)
- 90 Initialize hard-disk controllers
- 91 Initialize local-bus harddisk controllers
- 92 Jump to UserPatch2
- 93 Build MPTABLE for multi-processor boards
- 95 Install CD ROM for boot
- 96 Clear huge ES segment register
- 97 Fixup Multi Processor table
- 98 (1-2) Search for option ROMs. One long, two short beeps on checksum failure
- 99 Check for SMART Drive (optional)
- 9A Shadow option ROMs
- 9C Set up Power Management
- 9D Initialize security engine (optional)
- 9E Enable hardware interrupts
- 9F Determine number of ATA and SCSI drives
- A0 Set time of day
- A2 Check key lock
- A4 Initialize Typematic rate
- A8 Erase F2 prompt
- AA Scan for F2 key stroke
- AC Enter SETUP
- AE Clear Boot flag
- B0 Check for errors
- B2 POST done – prepare to boot operating system
- B4 (1) One short beep before boot
- B5 Terminate QuietBoot (optional)
- B6 Check password (optional)
- B9 Prepare Boot
- BA Initialize DMI parameters
- BB Initialize PnP Option ROMs
- BC Clear parity checkers
- BD Display MultiBoot menu
- BE Clear screen (optional)
- BF Check virus and backup reminders
- C0 Try to boot with INT 19
- C1 Initialize POST Error Manager (PEM)
- C2 Initialize error logging
- C3 Initialize error display function
- C4 Initialize system error handler
- C5 PnPnd dual CMOS (optional)
- C6 Initialize notebook docking (optional)
- C7 Initialize notebook docking late
- D2 Unknown interrupt
- E0 Initialize the chipset
- E1 Initialize the bridge
- E2 Initialize the CPU
- E3 Initialize system timer
- E4 Initialize system I/O
- E5 Check force recovery boot
- E6 Checksum BIOS ROM
- E7 Go to BIOS
- E8 Set Huge Segment
- E9 Initialize Multi Processor
- EA Initialize OEM special code
- EB Initialize PIC and DMA
- EC Initialize Memory type
- ED Initialize Memory size
- EE Shadow Boot Block
- EF System memory test
- F0 Initialize interrupt vectors
- F1 Initialize Real Time Clock
- F2 Initialize video
- F3 Initialize System Management Mode
- F4 (1) Output one beep before boot
- F5 Boot to Mini DOS
- F6 Clear Huge Segment
- F7 Boot to Full DOS
Original and reliable tables of POST codes can be found on the corresponding websites of BIOS manufacturers: “AMI” and “Award”. Sometimes POST code tables are provided in motherboard manuals.
1. Test of software-accessible processor registers (POST codes: 01, 02).
2. Checking the RAM regeneration period (POST code: 04).
3. Initialize the keyboard controller (POST code: 05).
4. Preliminary check of the performance of non-volatile memory (CMOS) and the condition of the CMOS battery (POST code: 07).
5. Initialization of chipset registers with default values (POST code: BE, hex).
6. Checking the presence and determining the size of RAM (POST code: C1, hex).
7. Determining the presence and size of external cache memory (POST code: C6, hex).
8. Checking the first 64 KB of RAM (POST code: 08).
9. Initialization of interrupt vectors (POST code: 0A, hex).
10. Checking the CMOS checksum (POST code: 0V, hex).
11. Detection and initialization of the video controller (POST code: 0D, hex).
12. Video memory check (POST code: 0E, hex).
13. Checking the BIOS checksum (POST code: 0F, hex).
14. Checking controllers and DMA page registers (POST codes: 10,
11, hex).
15. Checking the system timer (POST code: 14, hex).
16. Checking and initializing interrupt controllers (POST codes: 15...18, hex).
17. Initialization of expansion bus slots (POST codes: 20…2F, hex).
18. Determining the size and checking the main and extended memory (POST codes: 30, 31, hex).
19. Re-initialize the chipset registers in accordance with the values set in CMOS Setup (POST code: BF, hex).
20. Initialization of the FDD controller (POST code: 41, hex).
21. Initializing the HDD controller (POST code: 42, hex).
22. Initialization of COM and LPT ports (POST code: 43, hex).
23. Detection and initialization of the math coprocessor (POST code: 45, hex).
24. Checking whether a password is required (POST code: 4F, hex).
25. Initializing BIOS extensions (POST code: 52, hex).
26. Setting the Virus Protect, Boot Speed, NumLock, Boot Attempt parameters in accordance with the values set in CMOS Setup (POST codes: 60...63, hex).
27. Calling the operating system boot procedure (POST code: FF, hex).
As can be seen from the above sequence, the ability to display diagnostic messages on the monitor screen appears only after the video controller is initialized, and if the POST procedure stopped at one of the previous stages, then it is not possible to see at which one.
Analysis of computer errors using a diagnostic card (POST card)
1. Introduction
2. General description of POST card
4. Error code table
5. Description of sound signals
6. Reset a forgotten BIOS password
Introduction
The card is called POST (Power On Self Test - self-test card). Displays error codes when the operating system cannot boot or there is no image on the screen or no BIOS sounds.
When power is applied, the BIOS performs an accurate test of the circuit, memory, keyboard, video card, hard drive, then analyzes the system configuration. After the basic input/output system is initialized, the operating system loads.
The diagnostic card will not display data in the following cases:
1. The card is inserted into the motherboard without a CPU.
2. When the RST LED is lit.
General description of POST card
Description of luminous diodes:
LED | Type | Description |
RUN | Flicker | If the LED is on, the motherboard is turned on, it doesn't matter what codes are running |
CLK | BUS CLOCK | Lights up when power is supplied to the motherboard (usually without a processor) |
BIOS | Read BIOS | The LED turns on and off when power is supplied to the motherboard, when the processor is reading the BIOS |
IRDY | The manager is ready | LED turns on and off when there is a message |
O.S.C. | Flashing | Lights up when power is supplied to the motherboard, or if not, then the oscillating circuit crystal is broken |
FRAME | Frame period | It's on all the time. Turns on and off when there is a message |
RST | Reset | Lights up for half a second when you press the power or reset button. If the power is on, then it is worth checking RESET (shorted or broken). |
12V | Power | Lights up once when turned on, power is supplied, if it doesn’t light up it means a short circuit on the motherboard or no 12V. |
-12V | Nutrition | Same as "12V" |
5V | Nutrition | Same as "12V" |
-5V | Nutrition | Same as "12V" (-5V only for ISA slot) |
3V3 | Nutrition | Lights up when power is applied (PCI only), where there is 3.3V. If there is no standby voltage of 3.3V on the motherboard, it does not light up |
Error Code Table
Code | Award | AMI | Phoenix4.0/Tendy3000 |
00 | Code copying to specific areas is done/Passing control to INT 19h boot loader next. | ||
01 | Processor Test 1, Processor status (1FLAGS) verification. Test the following processor status flags: carry, zero, sign, overflow. The BIOS sets each flag, verifies they are set, then turns each flag off and verifies it is off. | CPU is testing the register inside or failed, please change the CPU and check it. | |
02 | Test All CPU Registers Except SS, SP, and BP with Data FF and 00 | Verify Real Mode | |
03 | Disable NMI, PIE, AIE, UEI, SQWV Disable video, parity checking, DMA Reset math coprocessor Clear all page registers, CMOS shutdown byte Initialize timer 0, 1, and2, including set EISA timer to a known state Initialize DMA controllers 0 and 1 Initialize interrupt controllers 0 and 1 Initialize EISA extended registers | Disable NMI, PIE, AIE, UEI, SQThe NMI is disabled. Next, checking for a soft reset or a power on condition | Disable Non-Mask-able interrupt (NMI) |
04 | RAM must be periodically refreshed to keep the memory from decaying. This refresh function is working properly | Get CPU type | |
05 | Keyboard Controller initialization | The BIOS stack has been built. Next, disabling cache memory. | DMA initialization in progress or failure |
06 | Reserved | Uncompressing the POST code next. | Initialized system hardware |
07 | Verifies CMOS is Working Correctly, Detects Bad Battery | Next, initializing the CPU data area | Disable shadow and execute code from the ROM |
08 | Early chip set initialization Memory presence test OEM chip set routines Clear low 64K memory Test first 64K memory | The CMOS checksum calculation is | Initialize chipset with with initial POST values |
09 | Cyrix CPU initialization Cach initialization | Set IN POST flag | |
0A | Initialize first 120 interrupt vectors with SPURIOUS-INT-HDLR and initialize INT 00h-1Fh according to INT-TBL | The CMOS checksum calculation is done. Linitializing the CMOS status register for date and time next | Initialize CPU registers |
0B | Test CMOS RAM Checksum. If bad, or INS Key Pressed, Load Defaults | The CMOS status register is initialized. Next. Performing any require initialization before the keyboard BAT command is issued | Enable CPU cache |
0C | Detect Type of Keyboard Controller and Set NUM LOCK Status | The keyboard controller input butter is free Next, issuing the BAT command to the keyboard controller | Initialize caches to initial POST values |
0D | Detect CPU Clock Read CMOS location 14h to find out type of video in use Detect and initialize video adapter | ||
0E | Test Video Memory, write sign-on message to screen Setup shadow RAM? Enable shadew according to setup | The keyboard controller BAT command result has been verified. Next, performing any necessary initialization after the keyboard controller BAT command test | Initialize I/O component |
0F | Test DMA Cont. 0; BIOS Checksum Test Keyboard Detect and initialization | The initialization after the keyboard controller BAT command test is done. The keyboard command byte is written next | Initialization of the local bus IDE |
10 | Test DMA Controller 1 | Test DMA The keyboard controller command byte is written. Next, issuing the Pin 23 and 24 Blocking and unblocking command | Initialize Power Management |
11 | Test DMA Page Registers | Next, checking if "End" or "Ins" keys were pressed during power on. Initializing CMOS RAM in every boot AMIBIOS POST option was set in AMIBCP or the "End" key was pressed | |
12 | Reserved | Next, disabling DMA controllers 1 and 2 and interrupt controllers 1 and 2 | Restore CPU control word during warm boot |
13 | Reserved | The video display has been disabled. Port B has been initialized. Next, initializing the chipset | initialize PCI Bus Mastering devices |
14 | Test 8254 Timer 0 Counter 2 | The 8254 timer test will begin next | |
15 | Verify 8259 Channel 1 interrupts by Turning Off and On the interrupt Lines | ||
16 | Verify 8259 Channel 2 interrupts by Turning Off and On the interrupt Lines | BIOS ROM checksum | |
17 | Turn Off interrupts Then Verify No Interrupt Msk Register is On | Initialize cache before memory Auto size | |
18 | Force an interrupt and Verify the interrupt and Verify the interrupt Occurred | 8254 timer initialization | |
19 | Test Stuck NMI Bits; Verify NMI Can Be Cited | The 8254 timer test is over. Starting the memory refresh test next | |
1A | Display CPU clock | The memory refresh line is toggling. Checking the 15 seconds on/off time next | |
1B | Reserved | ||
1C | Reserved | Reset Programmable interrupt Controller | |
1D | Reserved | ||
1E | Reserved | ||
1F | If EISA non-volatile memory checksum is good, execute EISA initialization If not, execute ISA tests an clear EISA mode flag Test EISA configuration memory Integrity (checksum & communication interface) | ||
20 | Initialize Slot O (System Board) | Test DRAM refresh | |
21 | Initialize Slot 1 | ||
22 | Initialize Slot 2 | Test 8742 Keyboard Controller | |
23 | Initialize Slot 3 | Reading the 8042 input port and disabling the MEGAKEY Green PC feature next. Making the BIOS code segment writable and performing any necessary configuration before initializing the interrupt vectors | |
24 | Initialize Slot 4 | The configuration required before interrupt vector initialization has completed. Interrupt vector initialization is about to begin | Set ES segment register to 4Gb |
25 | Initialize Slot 5 | Interrupt vector initialization is done. Clearing the password if the POST DIAG awitch is on | |
26 | 1. test the exceptional situation of protected of protected mode, check the memory of cpu and mainboard. 2. no fatal trouble, VGA displayed normally. If nonfateful trouble occurred, then display error message in VGA otherwise boot operating system, and code "26" is OK code, no any other codes to display |
1. read/write input, output port of 8042 keyboard; ready for revolve mode, continue to get ready for initialization of all data, check the 8042 chips on mainboard. 2. refer to the left |
1. enable A20 adress line, check the A20 pins of memory controlling chips, and check circuit, correlated to pins, in memory slot, may be A20 pin and memory pins are not in contact, or memory A20 pins bad. 2. refer to the left |
27 | Initialize Slot 7 | Any initialization before setting the video mode will be done next | |
28 | Initialize Slot 8 | Initialization before setting the video mode is complete. Configuring the monochrome mode and color mode settings next | Auto size DRAM |
29 | Initialize Slot 9 | Initialize POST Memory Manager | |
2A | Initialize Slot 10 | Initializing the different bus system, static, and output devices, if present | Clear 512 KB base RAM |
2B | Initialize Slot 11 | Passing control to the video ROM to perform any required configuration before the video ROM test | |
2C | Initialize Slot 12 | All necessary processing before passing control to the video ROM is done. Looking for the video ROM next and passing control to it | RAM failure on address line xxx* |
2D | Initialize Slot 13 | The video ROM has returned has returned control to BIOS POST Performing any required processing after the video ROM had control | |
2E | Initialize Slot 14 | Completed pest-video ROM test processing. If the EGA/VGA controller is not found, performing the display memory Read/write test next | RAM failure on data bits Xxxx* of low byte of memory bus |
2F | Initialize Slot 15 | The EGA/VGA controller was not found. The display memory read/write test is about to begin | Enable cache before system BIOS shadow |
30 | Size Base Memory From 256K to 640K and Extended Memory Above 1MB | The display memory read/write test passed. Look for retrace checking next | |
31 | Test Base Memory From 256K to 640K and Extended Memory Above 1MB | The display memory read/write test or retrace checking failed. Performing the alternate display memory read/write test next | |
32 | If EISA Mode, Test EISA Memory Found in Slots initialization | The alternate display memory read/write test passed. Looking for alternate display retrace checking next | Test CPU Bus-clock frequency |
33 | Reserved | Initialize Phoenix Dispatch manager | |
34 | Reserved | Video display checking is over. Setting the display mode next | |
35 | Reserved | ||
36 | Reserved | Warm start and shut down | |
37 | Reserved | The display mode is set. Displaying the power on message next | |
38 | Reserved | Initializing the bus input, IPL, general device next, if present | Shadow system BIOS ROM |
39 | Reserved | Displaying bus initialization error messages | |
3A | Reserved | The new cursor position has been read and saved. Displaying the Hit "Del" message next | Auto size cache |
3B | Reserved | The Hit "Del" message is displayed. The protected mode memory test is about to start | |
3C | Setup Enabled | Advanced configuration of chipset registers | |
3D | Detect if mouse is present, initialize mouse, install interrupt vectors | ||
3E | Initialize cache controller | ||
3F | Reserved | ||
40 | Display virus protect. Disable or Enable | Preparing the descriptor tables next | |
41 | Initialize Floppy Disk Drive Controller and any drives | Initialize extended memory for RomPilot | |
42 | Initialize Hard Drive Controller and any drives | The descriptor tables are prepared. Enteling protected mode for the memory test next | Initialize interrupt vectors |
43 | Detect and initialize Serial & Parallel Ports and Game Port | Entered protected mode. Enabling interrupts for diagnostics mode next | |
44 | Reserved | Interrupts enabled if the diagnostics switch is on. Initializing data to check memory wraparound at 0:0 next | |
45 | Detect and initialize math coprocessor | Data initialized. Checking for memory wraparound at 0: 0 and finding the total system memory size next | POST device initialization |
46 | Reserved | The memory wraparound test is done. Memory size calculation has been done. Writing patterns to tset memory next | Check ROM copyright notice |
47 | Reserved | The memory pattern has been to extended memory. Writing patterns to the base 640 KB memory | Initialize 120 support |
48 | Reserved | Patterns written in base memory. Determining the amount of memory below 1MB next | |
49 | Reserved | The amount of memory below 1MB has been found and verified. Determining the amount of memory above 1 MB memory next | |
4A | Reserved | ||
4B | Reserved | The amount of memory above 1MB has been found and verified. Checking for a soft reset and clearing the memory below 1MB for the soft reset next. If this is a power on situation, going to checkpoint 4Eh next | QuletBoot start (optional) |
4C | Reserved | The memory below 1MB has been cleared via a soft reset. Clearing the memory above 1MB next | Shadow video BIOS ROM |
4D | Reserved | The memory above 1MB has been cleared via a soft reset. Saving the memory size next. Going to checkpoint 52h next | |
4E | Reboot if Manufacturing Mode; if not, Display Messages and Enter Setup | The memory test started, but not as the result of a soft reset. Displaying the first 64KB memory size next | Display BIOS copyright notice |
4F | Ask Password Security (Optional) | The memory size display has started. The display is updated during the memory test. Performing the sequential and random memory test next | Initialize MultiBoot |
50 | Write All CMOS Values Back to RAM and Clear | The memory below 1MB has been tested and initialized. Adjusting the displayed memory size fot relocation and shadowing next | Display CPU type and speed |
51 | Enable Parity Checker. Enable NMI, Enable Cache Before Boot | The memory size display was adjusted for relocation and shadowing. Testing the memory above 1MB next | Initialize EISA board |
52 | Initialize Option ROMs from C8000h to EFFFFh or if FSCAN Enabled to F7FFFh | The memory above 1MB has been tested and initialized. Saving the memory size information next | Test keyboard |
53 | Initialize Time Value in 40h: BIOS Area | The memory size information and the CPU registers are saved. Entering real mode next | |
54 | Shutdown was successful. The CPU is in real mode. Disabling the Gate A20 line, parity, and the NMI next | Set key click if enabled | |
55 | |||
56 | Enable USB devices | ||
57 | The A20 address line, parity, and the NMI are disabled. Adjusting the memory size depending on relocation and shadowing next | ||
58 | The memory size was adjusted for relocation and shadowing. Clearing the Hit "DEL" message next | ||
59 | The Hit "DEL" message is cleared. The "WAIT..." message is displayed. Starting the DMA and interrupt controller test next | Initialize POST display service | |
5A | Display prompt Press F2 to enter SETUP | ||
5B | Disable CPU cache | ||
5C | Test RAM betweeb 512 and 640 kB | ||
60 | Setup virus protection (boot sector protection) functionality according to setup setting | The DMA page register test passed. Performing the DMA Controller 1 base register test next | Test extended memory |
61 | Try to turn on level 2 cach (if L2 cach already turned on in post 3D, this part will be skipped) Sat the boot up speed according to setup setting Last chance for chipset initialization Last chance for power management initialization (Green BIOS Only) Show the system configuration table | ||
62 | Set up the NUM lock. According to setup values Programm the NUM lock. Typematic rate & typematic speed according to setup setting | The DMA controller 1 base register test passed. Performing the DMA controller 2 base register test next | Test extended memory address lines |
63 | If there is any changes in the hardware configuration. Update the ESCD information (PnP BIOS only) Clear memory that have been used Boot system via INT 19h | ||
64 | Jump to UserPatch1 | ||
65 | The DMA controller 2 base register test passed. Programming DMA controller 1 and 2 next | ||
66 | Completed programming DMA controllers 1 and 2 initializing the 8259 interrupt controller next | Configure advanced cache registers | |
67 | Completed 8259 interrupt controller initialization | Initialize Multi Processor APIC | |
68 | |||
69 | Setup System Management Mode (SSM) area | ||
6A | Display external L2 cache size | ||
6B | Load custom defaults (optional) | ||
6C | Display shadow-area message | ||
6E | Display possible high address for UMB recovery | ||
6F | |||
70 | Display error message | ||
71 | |||
72 | |||
76 | Check for keyboard errors | ||
7C | Set up hardware interrupt vectors | ||
7D | Initialize intelligent System Monitoring | ||
7E | Initialize coprocessor if present | ||
7F | Extended NMI source enabling is in progress | ||
80 | The keyboard test has started. Clearing the output buffer and checking for stuck keys. Issuing the keyboard reset command next | Disable onboard Super I/O ports and IRQs | |
81 | A keyboard reset error or stuck key was found. Issuing the keyboard controller interface test command next | Late POST device initialization | |
82 | The keyboard controller interface test completed. Writing the command byte and initializing the circular buffer next | Detect and install external RS232 ports | |
83 | The command byte was written and global data initialization has completed. Checking for a locked key next | Configure non-MCD IDE controllers | |
84 | Locked key checking is over. Checking for a memory size mismatch with CMOS RAM data next | ||
85 | The memory size check is done. Displaying a soft error and checking for a password or bypassing WINBIOS Setup next | Initialize PC-compatible PnP ISA devices | |
86 | The password was checked. Performing any required programming before WINBIOS Setup next | ||
87 | The programming before WINBIOS Setup has completed Uncompressing the WINBIOS Setup code and executing the AMIBIOS Setup or WINBIOS Setup utility next | Configure Motherboard Configurable Devices (optional) | |
88 | Returned from WINBIOS Setup end cleared the screen. Performing any necessary programming after WINBIOS Setup next | Initialize BIOS Data Area | |
89 | The programming after WINBIOS Setup has completed. Displaying the power on screen message next | Enable Non-Maskable interrupts (NMis) | |
8A | Initialize Extended BIOS Data Area | ||
8B | The first screen message has been displayed. The "WAIT..." message is displayed. Performing the PS/2 mouse check and extended BIOS data area allocation check next | Test and initialize PS/2 mouse | |
8C | Programming the WINBIOS Setup options next | Initialize floppy controller | |
8D | The WINBIOS Setup options are programmed. Resetting the hard disk controller next | ||
8E | The hard disk controller has been reset. Configuring the floppy drive controller next | ||
8F | Determine number of ATA drives (optional) | ||
90 | Initialize hard-disk controllers | ||
91 | The floppy drive controller has been configured. Figuring the hard disk drive controller next | Initialize local-bus hard-disk controllers | |
92 | Jump to UserPatch2 | ||
93 | Build MPTABLE for multi-processor board | ||
95 | Initializing bus adapter ROMs from C8000h through D8000 | Install CD ROM for boot | |
96 | Initializing before passing control to the adapter ROM at C800 | ||
97 | Initialization before the C800 adapter ROM gains control has completed. The adapter ROM check is next | Fix up Multi Processor table | |
98 | The adapter ROM had control and now returned control to BIOS POST. Performing any required processing after the option ROM returned controlA | Search for option ROMs. One long, two short beeps on checksum failure | |
99 | Any initialization required after the option ROM test has completed. Configuring the timer data area and printer base address next | Check for SMART Drive (optional) | |
9A | Set the timer and printer base address. Setting the RS-232 base address next | Shadow option ROMs | |
9B | Returned after setting the RS-232 base address. Performing any required initialization before the coprocessor test next | ||
9C | Required initialization before the Coprocessor test is over. Initializing the Coprocessor next | Set up Power Management | |
9D | Coprocessor initialized Performing any required initialization after the Coprocessor test next | Initialize security engine (optional) | |
9E | Initialization after the Coprocessor test is complete. Checking the extended keyboard, keyboard ID, and NumLock key next. Issuing the keyboard ID command next | Enable hardware interrupts | |
9F | Determine number of ATA and SCSI drivers | ||
A0 | Set time of day | ||
A1 | Check key lock | ||
A2 | Displaying any soft error next | ||
A3 | The soft error display has completed. Setting the keyboard typmatic rate next | ||
A4 | The keyboard typematic rate is set. Programming the memory wait states next | Initialize typematic rate | |
A5 | Memory wait state programming is over. Clearing the screen and enabling parity and the NMI next | ||
A7 | NMI and parity enabled. Performing any initialization required before passing control to the adapter ROM at E000 next | ||
A8 | Initialization before passing control to the adapter ROM at E000h completed. Passing control to the adapter ROM at E000h next | Erase F2 prompt | |
A9 | Returned from adapter ROM at E000h control. Performing any initialization required after the E000 option ROM had control next | ||
A.A. | Initialization after E000 option ROM control has completed. Displaying the system configuration next | Scan for F2 key stroke | |
AB | Uncompressing the DMI data and executing DMI POST initialization next | ||
A.C. | Enter SETUP | ||
A.E. | Clear boot flag | ||
B0 | If interrupts Occurs in protected mode | The system configuration is displayed | Check for errors |
B1 | If unmasked NMI Occurs. Display Press F1 to Disable NMI, F2 Reboot | Copying any code to specific areas | Inform RomPilot about the end of POST |
B2 | POST prepare done to boot operating system | ||
B3 | |||
B4 | 1 One short beep before boot | ||
B5 | Terminate Quiet Boot (optional) | ||
B6 | Check password (optional) | ||
B7 | Initialize ACPI BIOS | ||
B8 | |||
B9 | Prepare Boot | ||
B.A. | Initialize SMBIOS | ||
BB | Initialize PnP Option ROMs | ||
B.C. | Clear parity checkers | ||
BD | Display MultiBoot menu | ||
BE | Program chipset registers with power on BIOS defaults | Clear screen (optional) | |
B.F. | Program the rest of the chipset "s value according to setup (later setup value program) If auto configuration is anabled, programmed the chipset with predefined values in the MODBINable Auto Table | Check virus and backup reminders | |
C0 | Turn off OEM specific cach, shadow Initialize standard devices with default values: DMA controller (8237); Programmable interrupt Controller (8259); Programmable interval Timer (8254); RTC chip | Try to boot with INT 19 | |
C1 | OEM Specific-Test to size On-Board memory | Initialize POST error manager (PEM) | |
C2 | Initialize error logging | ||
C3 | Test the first 256K DRAM Expand the compressed codes into temporary DRAM area including the compressed system BIOS & Option ROMs | Initialize error display function | |
C4 | Initialize system error handler | ||
C5 | OEM Specific-Early Shadow Enable for fast boot | PnPnd dual CMOS (optional) | |
C6 | External Cache Size Detection | Initialize note dock (optional) | |
C7 | Initialize note dock late | ||
C8 | Force check (optional) | ||
C9 | Extended checksum (optional) | ||
C.A. | Redirect int 15h to enable remote keyboard | ||
C.B. | Redirect int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk | ||
CC | Redirect int 10h to enable remote serial video | ||
CD | Re-map I/O and memory for PCMCIA | ||
C.E. | Initialize digitizer and display message | ||
D0 | The NMI is disable. Power on delay is starting. Next, the initialization code checksum will be verified | ||
D1 | Initializing the DMA controller, performing the keyboard controller BAT test, starting memory refresh, and entering 4GB flat mode next | ||
D2 | Unknown interrupt | ||
D3 | Starting memory sizing next | ||
D4 | Returning to real mode. Executing any OEM patches and setting the next stack | ||
D5 | Passing control to the uncompressed code in shadow RAM at E000: 0000h. The initialization code is copied to segment 0 and control will be transferred to segment 0 | ||
D6 | Control is in segment 0 Next, checking if "Ctrl" "Home" was pressed and verifying the system BIOS checksum. If either "Ctrl" "Home" was pressed or the system BIOS checksum is bad, next will go to checkpoint code E0h. Otherwise, going to checkpoint code D7h | ||
E0 | The onboard floppy controller if available is initialized. Next, beginning the base 512 KB memory test | Initialize the chipset | |
E1 | E1 Setup-Page E1 | Initializing the interrupt vector table next | Initialize the bridge |
E2 | E2 Setup-Page E2 | Initializing the DMA and interrupt controllers next | Initialize the CPU |
E3 | E3 Setup-Page E3 | Initialize system timer | |
E4 | E4 Setup-Page E4 | Initialize system I/O | |
E5 | E5 Setup-Page E5 | Check force recovery boot | |
E6 | E6 Setup-Page E6 | Enabling the floppy drive controller and Timer IRQs. Enabling internal cache memory | Checksum BIOS ROM |
E7 | E7 Setup-Page E7 | Go to BIOS | |
E8 | E8 Setup-Page E8 | Set Huge Segment | |
E9 | E9 Setup-Page E9 | Initialize Multi Processor | |
E.A. | EA Setup-Page EA | Initialize OEM special code | |
E.B. | EB Setup-Page EB | Initialize PIC and DMA | |
E.C. | EC Setup-Page EC | Initialize Memory type | |
ED | ED Setup-Page ED | Initializing the floppy drive | Initialize Memory size |
E.E. | EE Setup-Page EE | Looking for a floppy diskette in drive A: Reading the first sector of the diskette | Shadow boot block |
E.F. | EF Setup-Page EF | A read error occurred while reading the floppy drive in drive A: | System memory test |
F0 | Next, searching for the AMIBOOT.ROM file in the root directory | Initialize interrupt vectors | |
F1 | The AMIBOOT.ROM file is not in the root directory | Initialize Run Time Clock | |
F2 | Next, reading and analyzing the floppy diskette FAT to find the clusters occupied by the AMIBOOT.ROM file | Initialize video | |
F3 | Next, reading the AMIBOOT.ROM file, cluster by cluster | Initialize System Management Manager | |
F4 | The AMIBOOT.ROM file is not the correct size | Output one beep | |
F5 | Next, disabling internal cache memory | Clear Huge Segment | |
F6 | Boot to mini DOS | ||
F7 | Boot to full DOS | ||
FB | Next, detecting the type of flash ROM | ||
F.C. | Next, erasing the flash ROM | ||
FD | Next, programming the flash ROM | ||
FF | Flash ROM programming was successful. Next, restarting the system BIOS |
Description of sound signals
AMI BIOS Fatal Errors
1 beep | DRAM Refresh Failure. Try reseating the memory first. If the error still occurs, replace the memory with known good chips. |
2 beeps | Parity error in first 64K RAM. Try reseating the memory first. If the error still occurs, replace the memory with known good chips |
3 beeps | Base 64K RAM Failure. Try reseating the memory first. If the error still occurs, replace the memory with known good chips |
4 beeps | System timer failure |
5 beeps | Process failure |
6 beeps | Keyboard controller 8042-Gate A20 Error. Try reseating the keyboard controller chip. If the error still occurs, replace the keyboard chip. If the error persists, check parts of the system relating to the keyboard, e.g. try another keyboard, check to see if the system has a keyboard fuse |
7 beeps | Processor, Virtual Mode Exception Interrupt Error |
8 beeps | Display memory Read/Write test failure (non-fatal). Replace the video card or the memory on the video card |
9 beeps | ROM BIOS Checksum (32KB at F800:0) Failed. It is not likely that this error can be corrected by reseating the chips. Consult the motherboard supplier or an AMI product distributor for replacement part(s) |
10 beeps | CMOS shutdown register read/write error |
11 beeps | Cache memory error |
AMI BIOS beep codes (not fatal errors)
2 short | POST Failure-one or more of the hardware tests has failed |
1 long 2 short | An error was encountered in the video BIOS ROM, or a horizontal retrace failure has been encountered |
1 long 3 short | Conventional/Extended memory failure |
1 long 8 short | Display/Retrace test failed |
Award BIOS beep codes
1 short | No error during POST |
2 short | Any Non-fatal error, enter CMOS SETUP to reset |
1 long 1 short | RAM or motherboard error |
1 long 2 short | Video error, cannot initialize screen to display any information |
1 long 3 short | Keyboard controller error |
1 long 9 short | Flash RAM/EPROM (which on the motherboard) error. (BIOS error) |
long beep | Memory bank is not plugged well, or broken |
Phoenix BIOS beep codes
Sound codes | Description/What to check? |
1-1-1-3 | Verify real mode |
1-1-2-1 | Get CPU type |
1-1-2-3 | Initialize system hardware |
1-1-3-1 | Initialize chipset registers with initial POST values |
1-1-3-2 | Set in POST flag |
1-1-3-3 | Initialize CPU registers |
1-1-4-1 | Initialize cache to mitial POST values |
1-1-4-3 | Initialize I/O |
1-2-1-1 | Initialize Power management |
1-2-1-2 | Load alternate registers with initial POST values |
1-2-1-3 | Jump to User Patch0 |
1-2-2-1 | Initialize keyboard controller |
1-2-2-3 | BIOS ROM checksum |
1-2-3-1 | 8254 timer initialization |
1-2-3-3 | 8237 DMA controller initialization |
1-2-4-1 | Reset programmable interrupt controller |
1-3-1-1 | Test DRAM refresh |
1-3-1-3 | Test 8742 keyboard controller |
1-3-2-1 | Set ES segment to register to 4GB |
1-3-3-1 | 28 Autosize DRAM |
1-3-3-3 | Clear 512K base RAM |
1-3-4-1 | Test 512K base address lines |
1-3-4-3 | Test 512K base memory |
1-4-1-3 | Test CPU BUS-clock frequency |
1-4-2-4 | Reinitialize the chipset |
1-4-3-1 | Shadow system BIOS ROM |
1-4-3-2 | Reinitialize the cache |
1-4-3-3 | Autosize cache |
1-4-4-1 | Configure advanced chipset registers |
1-4-4-2 | Load alternate registers with CMOS values |
2-1-1-1 | Set initial CPU speed |
2-1-1-3 | Initialize interrupt vectors |
2-1-2-1 | Initialize BIOS interrupts |
2-1-2-3 | Check ROM copyright notice |
2-1-2-4 | Initialize manager for PCI options ROMs |
2-1-3-1 | Check video configuration against CMOS |
2-1-3-2 | Initialize PCI bus and devices |
2-1-3-3 | Initialize all video adapters in system |
2-1-4-1 | Shadow video BIOS ROM |
2-1-4-3 | Display copyright notice |
2-2-1-1 | Display CPU type and speed |
2-2-1-3 | Test keyboard |
2-2-2-1 | Set key click if enabled |
2-2-2-3 | 56 enable keyboard |
2-2-3-1 | Test for unexpected interrupts |
2-2-3-3 | Display prompt "press F2 to enter SETUP" |
2-2-4-1 | Test RAM between 512 and 640k |
2-3-1-1 | Test expanded memory |
2-3-1-3 | Test expanded memory address lines |
2-3-2-1 | Jump to user patch1 |
2-3-2-3 | Configure advanced cache registers |
2-3-3-1 | Enable external and CPU caches |
2-3-3-3 | Display extemal cache size |
2-3-4-1 | Display shadow massage |
2-3-4-3 | Display non-disposable segments |
2-4-1-1 | Display error massages |
2-4-1-3 | Check for configuration errors |
2-4-2-1 | Test real-time clock |
2-4-2-3 | Check for keyboard errors |
2-4-4-1 | Set up hardware interrupts vectors |
2-4-4-3 | Test coprocessor of present |
3-1-1-1 | Display onboard I/O ports |
3-1-1-3 | Detect and install external Rs232 ports |
3-1-2-1 | Detect and install external parallel ports |
3-1-2-3 | Re-initialize onboard I/O ports |
3-1-3-1 | Initialize BIOS data area |
3-1-3-3 | Initialize extended BIOS data area |
3-1-4-1 | Initialize floppy controller |
3-2-1-1 | Initialize hard-disk controller |
3-2-1-2 | Initialize local-bus hard-disk controller |
3-2-1-3 | Jump to userPatch2 |
3-2-2-1 | Disable A20 address line |
3-2-2-3 | Clear huge ES segment register |
3-2-3-1 | Search for option ROMs |
IBM BIOS beep codes
Sound codes | Description |
No beeps | No Power, Loose card or short |
1 short beep | Normal POST, computer is ok |
2 short beeps | POST error, review screen for error code |
continuous beep | |
Repeating short beep | No power, loose card, or short |
One long and one short beep | Motherboard issue |
One long and two short beeps | Video (EGA) display circuitry |
Three long beeps | Keyboard/keyboard card error |
One beep, blank or incorrect display | Video display circuitry |
Resetting a forgotten BIOS password
AMI passwords:
Other BIOS:
Phoenix BIOS: phoenix | Megastar: star |
Biostar Biostar: Q54arwms | Micron: sldkj754xyzall |
Compag: compag | Micronies: dn 04rie |
CTX international: CTX_123 | Packard Bell: bell9 |
Dell: Dell | Shuttle: space |
Digital Equipment: comprie | Siements Nixdorf: SKY FOX |
HP Vectra: hewlpack | Tinys: tiny |
IBM: IBM MBIUO sertafu | TMC:BIGO |
Reset BIOS password programmatically.
The CMOS ROM can be reset programmatically using the command line with the command debug(Works only up to Windows 7 version, does not work in 8).
Reset Award BIOS password:
C:\>debug
-o 70 34 "Enter"
-o 71 34 "Enter"
-q "Enter"
or
C:\>debug
-o 70 11 "Enter"
-o 71 11 "Enter"
-q "Enter"
Reset AMI BIOS password:
C:\>debug
-o 70 16 "Enter"
-o 71 16 "Enter"
-q "Enter"
or
C:\>debug
-o 70 10 "Enter"
-o 71 0 "Enter"
-q "Enter"
Reset Phoenix BIOS password:
C:\>debug
-o 70 ff "Enter"
-o 71 17 "Enter"
-q "Enter"
What it looks like on the command line:
The BIOS settings will be erased, so the next time the system boots, you may need to change the settings (for example, if your disk startup order is different, then you need to reassign, otherwise the system will not boot).
Hard reset CMOS BIOS with jumper
Usually, completing the first two steps is enough, just return the jumper to its original position. You can simply close the pins with a screwdriver if the jumper is missing. The pins are usually labeled on the motherboard: Clear CMOS, CL_CMOS, CRTC, CCMOS, CL_RTC, Clean CMOS, CMOS ROM Reset. Or you can simply remove the battery.
You can use the universal CMOS De-Animator utility to reset the BIOS settings programmatically. Can save settings to a file and restore them. Download from the official website CMOS De-Animator
And a small sign telling you which keys you can use to enter the BIOS settings: