Virtual memory. Architectural means of supporting virtual memory. Methods of organizing memory Associative memory of computers
General information and classification of memory devices
Lecture 2. Organization of computer memory.
Minisupercomputer and superminicomputer.
Small and microcomputers.
There are a large number of, relatively speaking, “small” applications of computers, such as automation of production control of products, data processing during experiments, receiving and processing data from a communication line, technological process control, control of machine tools and various digital terminals, small computational engineering tasks .
Currently, small and microcomputers are built into various “smart” devices (electricity meters, microwave ovens, washing machines, modems, sensors, etc.).
The classification does not have clear boundaries between the considered types of computers. Recently, two intermediate types have been distinguished.
Superminicomputers include high-performance computers containing one or more loosely coupled processors connected to a common backbone (common bus). It is typical for a superminicomputer that the speed of performing its arithmetic operations on floating point numbers is significantly lower than the speed of operation determined by a mixture of commands corresponding to information and logical queries. This type includes the IBM chess computer Deep Blue.
Minisupercomputers are simplified (particularly due to a shorter word) multiprocessor computers, most often with vector and pipeline processing tools, with high speed of performing operations on floating point numbers. This type includes computers with SMP (Symmetric multiprocessor) architecture.
| Memory devices can be classified according to the following criteria: · by type of storage elements · by functional purpose · by type of method of organizing circulation · by the nature of reading · by storage method · by method of organization By type of storage elements Semiconductor Magnetic Capacitor Optoelectronic Holographic Cryogenic By functional purpose RAM SRAM VZU ROM PROM | By the method of organizing circulation With sequential search With direct access With immediate access or Address Associative Stack Store By the nature of reading With destruction of information Without destruction of information By method of storage Static Dynamic By method of organization One-coordinate Two-coordinate Three-coordinate Two-three-coordinate |
By memory A computer is a set of devices used for storing, storing and issuing information. The individual devices included in this set are called storage devices or memories of one type or another.
The performance and computing capabilities of a computer are largely determined by the composition and characteristics of its memory. As part of a computer, several types of memory are used simultaneously, differing in the principle of operation, characteristics and purpose.
The main operations in memory are storing information in memory - record and retrieving information from memory - reading. Both of these operations are called access to memory.
When accessing memory, a certain unit of data is read or written - different for different types of devices. Such a unit could be, for example, a byte, a machine word, or a data block.
The most important characteristics of individual memory devices (storage devices) are memory capacity, specific capacity, and performance.
Memory capacity determined by the maximum amount of data that can be stored in it.
Specific capacitance is the ratio of the storage capacity to its physical volume.
Recording Density is the ratio of storage capacity to storage area. For example, a HDD with a capacity of up to 10 GB has a recording density of 2 Gbit per square meter. inch.
Memory performance is determined by the duration of the access operation, i.e. the time spent searching for the desired unit of information in memory and reading it ( read access time), or time to search for a place in memory intended for storing a given unit of information, and to record it in memory (access time when writing).
Duration of memory access (memory cycle time) when reading
where is the access time, determined by the time interval between the start of the reading operation until the moment when access to a given piece of information becomes possible; - the duration of the physical reading process itself, i.e. the process of detecting and recording the states of the corresponding storage elements or areas of the surface of the information carrier.
In some memory devices, reading information is accompanied by its destruction (erasure). In this case, the access cycle must contain the operation of restoring (regenerating) the read information in its original place in memory.
Duration of access (cycle time) when recording
where is the write access time, i.e., the time from the moment the write access begins until the moment when access to the storage elements (or areas of the media surface) into which recording is made becomes possible; - preparation time spent on bringing storage elements or areas of the surface of an information carrier to their original state for recording a specific unit of information (for example, a byte or a word); - time of entering information, i.e. changing the state of storage elements (parts of the surface of the medium). For the most part
The duration of the memory access cycle is taken to be
Depending on the access operations implemented in memory, they are distinguished: a) memory with random access (reading and writing data into memory is possible); b) memory for reading information only (“permanent” or “one-way”). Information is recorded in permanent memory during the process of its manufacture or configuration.
These types of memory correspond to the terms RAM (random access memory) and ROM (read only memory).
According to the method of organizing access, memory devices are distinguished with immediate (random), direct (cyclic) and sequential access.
In memory since direct (arbitrary) With access, the access time, and therefore the access cycle, do not depend on the location of the memory section from which information is read or written to. In most cases, direct access is realized using electronic (semiconductor) memories. In such memories, the access cycle is usually 70 nanoseconds or less. The number of bits read or written in direct access memory in parallel in time during one access operation is called sample width.
The other two types of memory use slower electromechanical processes. In devices direct access memory, which include disk devices, due to the continuous rotation of the storage medium, the ability to access a certain section of the storage medium for reading or writing is repeated cyclically. In such memory, access time usually ranges from a few fractions of a second to several tens of milliseconds.
In memory with sequential access sequential viewing of sections of the storage medium is carried out until the desired section of the storage medium takes a certain initial position. A typical example is storage on magnetic tapes, the so-called. streamers ( streamer). In unfavorable cases of information location, access time can reach several minutes.
A good example of a tape drive is the use of an ARVID adapter with a VHS video recorder. The capacity of this drive is 4GB/180min.
Storage devices also differ in the functions performed in the computer, depending in particular on the location of the storage device in the computer structure.
Requirements for memory capacity and speed are contradictory. The higher the performance, the more technically difficult it is to achieve and the more expensive it is to increase memory capacity. The cost of memory makes up a significant portion of the total cost of a computer. Therefore, computer memory is organized in the form of a hierarchical structure of storage devices with different speeds and capacities. In general, a computer contains the following types of memory, in descending order of speed and increasing capacity.
The hierarchical structure of memory makes it possible to cost-effectively combine the storage of large amounts of information with rapid access to information during processing.
Table 2.1.
RAM or main memory(OP) is a device that serves to store information (program data, intermediate and final processing results) directly used in the process of performing operations in the arithmetic-logical unit (ALU) and control unit (CU) of the processor.
In the process of information processing, there is close interaction between the processor and the OP. Program commands and operands are received from the OP to the processor, on which the operations specified by the command are performed, and intermediate and final processing results are sent from the processor to the OP for storage.
The characteristics of the operating system directly affect the main indicators of the computer and, first of all, the speed of its operation. Currently, RAM has a capacity from several MB to several GB and an access cycle of about 60 ns or less. OP storage devices are manufactured on integrated circuits with a high degree of integration (semiconductor memories).
Recently, a number of companies have announced the start of serial production of dynamic memory chips with a capacity of 1GB. The recognized leader is Samsung. The most popular product today can be considered 64 MB chips. In the coming year, 128MB and 256MB chips are expected to be widely used.
In a number of cases, the speed of the OP turns out to be insufficient, and the machine has to include a SOP (buffer or cache memory of several hundred or thousand kilobytes with an access cycle of several nanoseconds. Such SOPs are executed on static memory chips. The performance of the cache must correspond to the speed of the arithmetic -logical and control devices of the processor. Super-RAM (buffer) memory is used for intermediate storage of program sections and data groups read by the processor from the OP, as working cells of the program, index registers, for storing service information used in controlling the computing process. It acts as a coordinating memory. a link between the high-speed logical devices of the processor and the slower operating system.
High-speed memories with random access and direct access are used as OP and SOP.
Typically, the capacity of the OP is insufficient to store all the necessary data in the computer. Therefore, the computer contains several memory devices with direct access on disks (the capacity of one memory device on HDD disks is 1 - 30 GB) and several memory devices with sequential access on magnetic tapes (the capacity of one memory device is 4 - 35 GB).
RAM, together with SOP and some other specialized processor memories, form internal memory Computer (Fig. 4.1). Electromechanical memory devices form external memory Computers, and that’s why they themselves are called external storage devices(VZU).
A storage device of any type consists of a storage array that stores information, and blocks that serve to search the array, write and read (and in some cases, regenerate) information.
A random access memory device, as a rule, contains many identical storage elements forming a storage array (SM). The array is divided into individual cells; each of them is designed to store binary code, the number of bits in which is determined by the width of the memory sample (in particular, it can be one, half or several machine words). The method of organizing memory depends on the methods of placing and searching for information in the storage array. Based on this feature, they distinguish between address, associative and stack (store) memories.
Address memory. In memory with an address organization, the placement and search of information in the memory is based on the use of the storage address of a word (number, command, etc.). The address is the number of the ZM cell in which this word is located.
When writing (or reading) a word into a memory, the command initiating this operation must indicate the address (cell number) at which the recording (reading) is performed.
A typical address memory structure contains a storage array of N-bit cells and its hardware frame, which includes an address register RgA having k (k» log N) digits, information register RGI, address sample block BAV, sense amplifier block BUS, block of bit amplifiers-formators of recording signals BUZ and memory management unit BUP.
By address code in RgA BAV generates signals in the corresponding memory cell that allow reading or writing a word in the cell.
The memory access cycle is initiated by an entry into BUP from outside the signal Appeal. The general part of the circulation cycle includes admission to RgA from the address bus SHA address and reception BUP and decoding of the control signal Operation, indicating the type of operation requested (read or write).
Further when reading BAV decrypts the address, sends read signals to the ZM cell specified by the address, while the code of the word written in the cell is read by the BUS reading amplifiers and transmitted to RGI. The read operation is completed by issuing a word from RGI to the output information bus SHIVYH.
When recording, in addition to performing the above general part of the access cycle, the word being written is received from the input information bus SHIVh And RGI. Then to the selected BAV cell is written a word from RGI.
Control unit BUP generates the necessary sequences of control signals that initiate the operation of individual memory nodes.
Associative memory. In this type of memory, the search for the necessary information is carried out not by address, but by its content (by associative characteristics). In this case, the search by an associative characteristic (or sequentially by individual bits of this characteristic) occurs in parallel in time for all cells of the storage array. In many cases, associative search can significantly simplify and speed up data processing. This is achieved due to the fact that in memory of this type, the operation of reading information is combined with the execution of a number of logical operations.
A typical structure of associative memory is shown in Fig. 4.3. The storage array contains N (n+1)-bit cells. To indicate the cell's occupancy, the nth service digit is used (0 - the cell is free, 1 - a word is written in the cell).
| Rice. 2.2. Structure of associative memory |
By input information bus SHIVh to the associative attribute register RgAP bits 0..n-1 receive an n-bit associative request, and the mask register RgM- search mask code, with n-digit RgM is set to 0. Associative search is performed only for a set of bits RgAP, which correspond to 1 in RgM(unmasked bits RgAP). For words in which the digits in the digits coincide with the unmasked digits RgAP, combinational circuit KS sets the corresponding bits of the match register to 1 RgSV and 0 in the remaining digits. So the value j-th category in RgSV is determined by the expression
РгСв(j)=
Where RgAP[i], RgM[i] And ZM[j,i] - values i-th category accordingly RgAP, RgM And j-and cells ZM.
Combination scheme for generating the result of an associative appeal FS forms from a word formed in RgSV, signals a 0 , a 1 , a 2 , corresponding to cases of absence of words in ZM, satisfying the associative criterion, and the presence of one (or more) such words.
Content generation RgSV and signals a 0 , a 1 , a 2 by content RgAP, RgM And ZM called association control operation. This operation is part of the read and write operations, although it has its own meaning.
When reading, the association is first checked according to the associative feature in RgAP. Then, when a 0 = 1, the reading is canceled due to the lack of the required information; when a 1 = 1, it is read into RGI found word, with a 2 = 1 in RGI a word is read from the cell that has the lowest number among the cells marked 1 y RgSV. From RGI the read word is given out on SHIVYH.
When recording, a free cell is first found. To do this, an association check operation is performed when RgAP= 111...10 and RgM= 00...01, with free cells marked 1 in RgSV. The free cell with the lowest number is selected for recording. It records the word received from SHIVh V RGI.
Using the association control operation, you can, without reading words from memory, determine by content RgSV, how many words are in memory that satisfy an associative criterion, for example, implement queries like how many students in a group have an excellent grade in a given discipline. When using appropriate combinational circuits, quite complex logical operations can be performed in associative memory, such as searching for a larger (smaller) number, searching for words within certain boundaries, searching for the maximum (minimum) number, etc. Associative memory is used, for example, in hardware dynamic distribution of OP.
Note that associative memory requires storage elements that can be read without destroying the information recorded in them. This is due to the fact that during associative search, reading is carried out throughout ZM for all unmasked bits and there is no place to store information that is temporarily destroyed by reading.
Stack memory, just like associative, is addressless. Stack memory can be considered as a collection of cells forming a one-dimensional array in which neighboring cells are connected to each other by bit word transfer circuits. A new word is written to the top cell (cell 0), while all previously written words (including the word that was in cell 0) are shifted down to adjacent cells with numbers larger by 1. Reading is possible only from the top (zero) memory cell, and if reading with deletion is performed, all other words in memory are shifted upward to adjacent cells with higher numbers. In this memory, the order in which words are read follows the rule: last in, first out. A number of devices of this type also provide for the operation of simply reading a word from the zero cell (without deleting it and shifting the word in memory). Sometimes stack memory is provided with a stack counter SchSt, showing the number of words stored in memory. Signal SchSt= 0 corresponds to an empty stack, SchSt= N- 1 - full stack.
Typically, stack memory is organized using address memory. In this case, there is usually no stack counter, since the number of words in memory can be determined by the stack pointer. Stack memory is widely used when processing nested data structures, when executing addressless commands and interrupts.
Architectural organization of a computer processor
The processor occupies a central place in the computer architecture, managing the interaction of all the main components that make up the computer. It directly processes information, and software control of this process deciphers and executes program commands, organizes access to random access memory (RAM), and initiates operations when necessary input/output and operation of peripheral devices, perceives and processes requests coming from both computer devices and the external environment (organization of the interrupt system). The execution of each command consists of the execution of smaller operations - microcommands that perform certain elementary actions. The set of microinstructions is determined by the command system and the logical structure of a particular computer. Thus, each computer command is implemented by a corresponding microprogram stored in a read-only memory device (ROM). In some computers (primarily specialized ones), all or part of the commands are implemented in hardware, which makes it possible to increase their performance at the expense of losing a certain part of the flexibility of the machine’s command system. Both one and the second method of implementing computer commands have their pros and cons.
The microprogramming language is designed to describe digital devices operating at the register level. It has simple and visual means of describing machine words, registers, buses and other basic elements of a computer. Taking into account the above, the hierarchy of languages for describing the computing process on a computer can be represented, in the general case, at four levels: (1) Boolean operation (functioning of combinational drugs) => (2) micro-instruction (functioning of computer nodes) => (3) command ( functioning of the computer) => (4) operator of the computer (description of the algorithm of the problem being solved). To determine the timing relationships between microcommands, a time unit (cycle) is set during which the longest microcommand is executed. Therefore, the execution of one computer command with clock pulses generated by a special processor device - a clock generator; the clock frequency (measured in MHz) largely determines the speed of the computer. Naturally, for other classes of computers this indicator is differently associated with productivity, determined by such additional factors as.
Memory access width,
Sampling time
Bit capacity,
Architecture of the processor and its coprocessors,
An enlarged diagram of the central processing unit (CPU) of some formal computer is presented in the figure, which shows only its main blocks: control registers (UR), control unit (CU), ROM, arithmetic-logical unit (ALU), register memory (RM), cache memory and interface unit (IB). Along with the above, the CPU contains a number of other blocks (interrupts, OP protection, monitoring and diagnostics, etc.), the structure and purpose of which are not discussed here. The control unit generates a sequence of control signals that initiate the execution of the corresponding sequence of microcommands (located in ROM) that implement the current command. Along with this, the control unit coordinates the functioning of all computer devices by sending control signals and data exchange to the CPU<->OP, information storage and processing, user interface, testing and diagnostics, etc. Therefore, it is advisable to consider the control unit as a separate CPU block; however, in practice, most control circuits are distributed throughout the computer. They are connected by a large number of control lines that transmit signals to synchronize operations in all computer devices and receive signals about their status. The UR block is designed for temporary storage of control information and contains registers and counters that participate together with the CU in controlling the computational process; the CPU state register, program (SSP), program counter (SC) is a register that stores the address of the executed command in the OP (during execution current instruction, its contents are updated to the address of the next instruction), the command register (RK) contains the command being executed (its outputs are connected to control circuits that generate time-distributed signals necessary for executing commands)
The RP block contains small-volume registers of extra-random memory (higher speed than OP), which allow increasing the performance and logical capabilities of the CPU. These registers are used in instructions by abbreviated register addressing (only register numbers are indicated) and serve to store operands, operation results, as base and index registers, stack pointers, etc. In some CPUs, base and index registers are part of the UT block, like As a rule, RP is performed in the form of high-speed semiconductor integrated memory devices
The ALU block is used to perform arithmetic and logical operations on data coming from the OP and stored in the RP, and operates under the control of the control unit. The ALU performs arithmetic operations on binary numbers with fixed and floating points, on decimal numbers, and processes symbolic information on words of fixed and variable length. Logical operations are performed on individual bits, groups of bits, bytes and their sequences. The type of operation performed by the ALU is determined by the current command of the currently running program; more precisely, the ALU is used to perform any operation assigned to it by the control unit. In the general case, the information processed by a computer consists of words containing a fixed number n of bits (for example, n = 8, 16, 32, 64, 128 bits). In this case, the ALU must be able to perform operations on n-bit words; the operands come from the OP to the ALU registers, and the control unit indicates the operation that needs to be performed on them; the result of each arithmetic-logical operation is stored in a special adder register, which is the main register for arithmetic-logical operations.
The adder is connected to gate circuits to perform the necessary operations on its contents and the contents of other registers. Some computers have several adders; if the number is greater than 4, they are allocated to a special group of general purpose registers (GPR). Structurally, the ALU is executed on one or several LSIs/VLSIs, while the CPU may have one universal-purpose ALU or several specialized ones for certain types of operations. In the latter case, the structural complexity of the CPU increases, but its performance increases due to specialization and simplification of the calculation schemes for individual operations. This approach is widely used in modern general-purpose computers and supercomputers to increase their performance. Despite the different classes of computers, their ALUs use general principles for performing arithmetic-logical operations. The differences relate to the circuit design solutions for organizing the ALU and the principles of implementation of the operation, ensuring the acceleration of their execution.
The interface unit (IB) ensures the exchange of information between the CPU and the OP and the protection of sections of the OP from unauthorized access for the current program, as well as communication between the CPU and peripheral devices and other external devices (DW), which can be other processors and computers. . In particular, the IB contains two registers that provide communication with the OP - the memory address register (MAR) and the memory data register (RDR). The first register is used to store the address of the OP cell with which data is exchanged, and the second contains the actual exchange data. The control and diagnostic unit (MCD) is designed to detect failures and failures of CPU nodes, restore the operation of the current program after failures and localize faults in the event of failures.
Taking into account the above, let us present a general scheme for executing programs on a processor. The execution of a program located in the OP begins with the address of its first command being sent to the CS, the contents of the CS are sent to the RAP, and a read control signal is sent to the OP. After some time (corresponding to the access time to the OP), the addressed word (in this case, the first command of the program) is extracted from the OP and loaded into the RDP, then the contents of the RDP are sent to the SC. At this stage, the command is ready for decoding its command and execution. If the instruction contains an operation that must be performed by the ALU, then the required operands must be obtained. If the operand is in the OP (and it may also be in the UR), it must be fetched from memory. To do this, the address of the operand is sent to the RPA and the read cycle begins. The operand selected from memory in the RPA can be transferred to the ALU. Having thus selected one or more operands, the ALU can perform the required operation, storing its result in one of the RONs. If the result of an operation needs to be stored in the OP, it must be sent to the RAP. The address of the cell in which the result must be placed is sent to the RAP and the recording cycle begins. Meanwhile, the contents of the CS are incremented, indicating the next command to be executed. Thus, as soon as the execution of the current command is completed, fetching for the execution of the next command of the program can immediately begin.
In addition to transferring data between the OP and the CPU, it is necessary to ensure the exchange of data with the host, which is done by machine instructions that control input/output. The natural order of program execution may be disrupted when an interrupt signal is received. An interrupt is a service request that is handled by the CPU executing the corresponding interrupt routine (ISR). Since an interrupt and its processing can change the internal state of the CPU, it is stored in the OP before the POP starts operating. State preservation is achieved by sending the contents of the RK, UR and some control information to the OP. Once the POP completes, the CPU state is restored, allowing execution of the interrupted program to continue.
Memory with associative access or associative memory differs from other types of memory in that access to its cells is carried out not at a specific address, but at content memory cells. In fact, associative memory works like a search system, capable of finding information according to a given pattern. The basis of associative memory is associative storage devices(AZU), which, like most operational memory, are volatile and are implemented in the form of semiconductor chips (chip sets).
The principle of operation of the ASU is explained by the diagram presented in Fig. 3.8. The storage array, as in addressable memories, is divided into m- bit cells, the number of which n. As a rule, the ASU includes:
· storage array (SM);
· register of associative characteristics (RgAP);
· mask register (RMM);
· register of address indicators with comparison circuits at the input.
There may be other elements in the ACS, the presence and functions of which are determined by the way the ACS is used.
Rice. 3.8. Associative storage device
Retrieving information from the AMS occurs as follows. A search pattern is transmitted to the register of associative features from the control device - code of the required information(sometimes called comparand). The code can have an arbitrary number of digits - from 1 to m. If the feature code is used in its entirety, then it enters the comparison circuit without changes, but if it is necessary to use only part of the code, then unnecessary bits are masked using the mask register. Before starting the search for information in the ASU, all bits of the address indicator register are set to the state 1 .After this, the first digit of all cells of the storage array is polled, and the contents are compared with the first digit of the associative characteristics register. If the contents of the first digit i th cell does not coincide with the contents of the first digit of RgAP, then the corresponding digit of the address indicator register T i reset to state 0 , if it matches – digit T i remains 1 . Then this operation is repeated with the second, third and subsequent digits until a comparison has been made with all RGAP digits. After bitwise polling and comparison in the state 1 those bits of the address indicator register that correspond to cells containing information that matches that recorded in the associative characteristics register will remain. This information can be read in the sequence determined by the control device.
Note that the time of searching for information in the SM based on an associative sign depends only on the number of digits of the attribute and on the speed of polling the digits, but is completely independent of the number of SM cells. This determines the main advantage of the memory storage unit over the address storage unit: in the address storage unit, during the search operation, it is necessary to enumerate all the cells of the storage array. In addition, there are implementations of the memory system that search simultaneously over all digits of all words written into memory, i.e. The search time in such devices does not exceed the memory cycle time.
New information is recorded in the ZM without specifying the cell number. Typically, one of the bits of each cell is used to indicate its occupancy, i.e. if the cell is free for writing, then this bit contains 0 , and if you’re busy, - 1 . Then, when new information is written to the RAM, the sign is set 0 in the corresponding digit of the register of associative characteristics, and all cells of the ZM that are free for writing are determined. The control device places new information in one of them.
Often, ASDs are built in such a way that, in addition to associative, direct addressing of data is also allowed, which provides certain convenience during operation.
It should be noted that the storage elements of the RAM, unlike the elements of the addressable memory, must not only store information, but also perform certain logical functions, therefore they allow searching not only by the equality of the cell contents to a given characteristic, but also by other conditions: the cell contents are greater (less than) comparand, and also greater than or equal to (less than or equal to).
The above-mentioned properties of the RAM characterize the advantages of the RAM for information processing. The formation of several streams of identical information using AMS is quick and simple, and with a large number of operational elements, high-performance systems can be created. We must also take into account the fact that on the basis of associative memory, a change in the location and order of information can be easily realized. Thanks to this, AMS is an effective means of generating data sets.
Research shows that a number of tasks, such as processing radar information, pattern recognition, processing various images and other tasks with a matrix data structure, are effectively solved by associative systems. In addition, programming such tasks for associative systems is much simpler than for traditional ones.
Unfortunately, memory devices with associative access have high manufacturing complexity and cost, exceeding similar indicators of both dynamic and static RAM. Associative memory is the basis for the construction of parallel associative systems, as well as for computers controlled by data flow. Associative access is most widely used in cache memory subsystems.
Cache memory
For the first time, a two-level memory structure was proposed by M. Wilkes in 1965 during the construction of the Atlas computer. The essence of the approach was to place a small, high-speed buffer memory between the CPU and OP. During the operation of the computer, those sections of the OP that are being accessed are copied into the buffer memory. Due to compliance with the principle of locality in circulation, a significant gain in performance is obtained.
The new type of memory is called cache memory(from English cache- “cache, refuge”), since such memory is hidden, “invisible” to the CPU, which cannot directly access it. In turn, the programmer may not even know about the existence of cache memory. In serial computers, cache memory was first used in systems model 85 of the IBMS/360 family. Today, cache memory is present in any class of computer, and often has a multi-level structure.
All the terms that were defined earlier can be used for cache memory, although the word " line» ( line) is often used instead of the word " block» ( block).
As a rule, cache memory is built on the basis of ultra-fast and expensive static RAM, while its speed is 5-10 times higher than the speed of the OP, and its volume is 500-1000 times less. Note that increasing the cache memory size in relation to the RAM capacity is hampered not only and not so much by the high cost of static RAM. The fact is that as the cache memory capacity increases, the complexity of the control circuits increases, which, in turn, leads to a decrease in performance. Numerous studies have shown that the specified ratio of cache memory and RAM volumes is optimal and will be maintained during the development of computers as the speed of both types of memory increases.
As already mentioned, the CPU does not have direct access to the cache memory. A special controller is responsible for organizing the interaction between the CPU, OP and cache memory. The entire OP is divided into blocks of a fixed size, while the highest part of the OP address determines block address, and the younger part is address of the word inside the block. The exchange of information between the OP and cache memory is carried out in blocks. The cache memory also has its own internal addressing, and each block read from the OP is placed in the cache memory at a specific location. block address in cache memory. Cache blocks are often called lines or cache lines.
If the block being requested by the CPU is already in the cache, then its reading is completed when the cache is accessed. Thus, when providing access to an address, the controller must first determine whether there is a copy of the block containing that address in the cache, and, if so, determine at which cache address that block begins. The controller receives this information using address translation mechanism. The complexity of this mechanism depends on placement strategies, which determines where in the cache memory each OP block should be placed.
No less important is the question of at what point a copy of the block from the OP should be placed in the cache memory. This issue can be resolved using sampling strategies.
When writing to cache memory, there are several methods for replacing old information, which are determined by main memory update strategy.
A situation often arises when, despite fetching the required block from the OP, there is no room in the cache memory to accommodate it. In this case, you need to select one of the cache lines and replace it with a new block. The method for determining which cache line to delete is called replacement strategy.
Placement Strategies
There are the following ways to place data in cache memory:
· direct distribution;
· completely associative distribution;
· partially (multiple) associative distribution.
Let's say the address bus width is n, then the capacity of the OP V OP = 2 n words Without loss of generality, we define the size of the cache line to be 256 words, thus the entire OP will be divided into 2n-8 blocks. The OP's address is senior n-8 bits will determine the address of the block, and the low byte will determine the address of the word in the block. Let the cache capacity V cache 1024 times less than the OP capacity, i.e. V cache = 2 n-10 words or 2 n-18 blocks (cache lines).
Direct distribution
If each block of main memory has only one fixed location where it can appear in the cache, then such a cache is called Directly allocated cache(direct mapped cache). This is the simplest organization of cache memory, in which the low-order bits of the block address are simply used to map the addresses of OP blocks to cache addresses. Thus, all OP blocks that have the same low-order bits in their address fall into one cache line, i.e.
(cache line address) = (OP block address) mod (number of blocks in cache memory)
In our example, the cache line address c will be junior n-18 OP block address bit (see Fig. 3.9). The conversion of the OP block address to the cache line address is carried out by fetching these minor n-18 bit. Any of the 1024 OP blocks that have the same n-18 least significant bits These blocks will differ from each other by the most significant 10 bits t, called tag. In order to determine which OP block is currently stored in cache memory, another memory is used - the so-called tag memory (tag memory). Tag memory is addressed word by word, with each word having a size equal to the size of the tag. Tag memory capacity is the product of the tag size and the total number of cache lines, for our example it is 10·2 n-18 bit. The tag memory address is the cache line address With. Unlike tag memory, the memory that stores cached blocks is called data memory. The data memory is addressed word by word, its address is formed from the address of the cache line and the address of the word inside the block (cache line).
Rice. 3.9. Memory address structure for direct allocation
Rice. 3.10. Directly allocated cache organization
When accessing A the th address of the OP (Fig. 3.10) minor n-18 block address bit (field c), where this address is contained, are used as the cache line address. At the address of the cache line, the tag is read from the tag memory (field t). In parallel, the data memory is accessed using n-10 least significant bits of the address A(fields c And w). If the read tag and the most significant 10 bits of the address A match, this means that the block containing the address A, exists in the data memory, and the accessed word stores a copy A-th address of the OP.
If the tag is different from the most significant 10 bits of the address A, then a block containing the address is read from main memory A, and a cache line whose address is determined by the field is removed from the cache memory c(younger n-18 bits) addresses of the block being read. The block read from the OP is placed in place of the deleted cache line, and the corresponding tag in the tag memory is updated.
The advantage of direct allocation is the ease of implementation, however, due to the fact that the cache line address is uniquely determined by the address of the OP block, there is a high probability of concentration of block areas in some part of the cache memory. Replacement of blocks in this part will occur quite often, while at the same time other areas of the cache memory may be idle. In such a situation, the effectiveness of the cache memory is noticeably reduced.
Associative memory
They say that memory rests on three pillars: associations, imprinting, repetition. But is it necessary to adhere to this model? Clever readers will easily see an analogy with ancient ideas about the world order and about the Earth having a flat surface. But is it necessary to adhere to this model? However, as long as the old model suits you, you can successfully use it in everyday practice.
Associations are invisible clues that firmly connect what we already remember well with what we need to consolidate in memory.
Associative memory Can And need to develop and train. When making conscious efforts, the search for associations will happen much faster, and over time, the skill can move to an unconscious level, associations will appear by themselves and remembering information will become easier and easier.
But enough theory, it’s time to move on directly to simple and completely easy exercises!
So, you have read 50 words, imagining the corresponding images as brightly as possible, in color and movement. Now try to connect all the words into one long story or several short ones: cat, house, car, apple...
Key
A white-and-red CAT entered a red brick HOUSE, walked into a built-in garage, got into a crimson CAR, drove onto the freeway and began, steering the wheel with her left paw, to gnaw on a green APPLE, holding it with her right paw.
There is no need to remember words at this stage of memory development. You will do this a little later, easily and playfully. Now I do not recommend overloading yourself with complex exercises. Do you want to achieve very high memory levels? For most people, it is more effective to move by increasing the level of difficulty little by little, but regularly.
This text is an introductory fragment. From the book Psychology of Intelligence and Giftedness author Ushakov Dmitry ViktorovichModes of creative thinking, associative network and distributed attention Ideas of mechanisms that can be compared with the intuitive pole of thinking in modern psychology go back to the works of S. Mednik. In the early 1960s he proposed that individual
author Muller StanislavPart I. How to double your memory in forty-five minutes, or Introduction to holographic memory Where it all began... Several years ago, after finishing the last lesson on memory development, one of the students makes claims regarding the results
From the book Unlock Your Memory: Remember Everything! author Muller StanislavAssociative memory They say that memory is based on three pillars: association, imprinting, repetition. But is it necessary to adhere to this model? Clever readers will easily see an analogy with ancient ideas about the world order and about the Earth having a flat
From the book Unlock Your Memory: Remember Everything! author Muller StanislavAssociative memory The same game (or exercise, as you wish) for associative linking words together, but only with the participation of touch sensations. You come up with one story that includes all fifty words, or several short ones, which at first even
From the book Unlock Your Memory: Remember Everything! author Muller StanislavAssociative memory The same game (or exercise) for associating words together, but with sounds and touches. You come up with one or more stories that include fifty words. We skip difficult words in the same way. Although, if there is a desire and
From the book Unlock Your Memory: Remember Everything! author Muller StanislavAssociative memory Come up with one story containing all fifty words, or several short ones. Now we don’t skip difficult words. Composing a story should no longer be difficult for you. Remembering words or stories at this stage of development of associative
author Muller StanislavPart I How to double your memory in 45 minutes, or an introduction to holographic memory “At the beginning of glorious deeds...” Several years ago, after finishing the last lesson on memory development, one of the students made a complaint to me: “Stanislav, people come to you.” , to
From the book Remember Everything [Secrets of Super Memory. Training book] author Muller StanislavAssociative memory They say that memory is based on three pillars: associations, imprinting, repetition. But is it necessary to adhere to this model? Clever readers will easily see an analogy with ancient ideas about the world order and about the Earth having a flat surface.
From the book Let's start over, or How to see your Tomorrow author Kozlov Nikolay IvanovichMemory of the past and memory of the future My colleague psychologists, memory researchers, suggest that the reserves of our memory are practically inexhaustible. Our head is enough for us to remember everything and always: that random conversation on the street, and the swaying of every branch of that
From the book Psychology of Adulthood author Ilyin Evgeniy PavlovichAssociative methodology for diagnosing personal maturity Authors: E. V. Kalyaeva, T. V. Prokofieva Instructions. A number of words are offered to your attention. Think about what associations each of these words evokes, write them down. 35 characteristics are offered that reveal the concept
From the book Developmental Psychology [Research Methods] by Miller Scott“Everyday” memory and long-term memory Let’s consider two more questions related to the topic “Memory”. Until now, the main attention has been paid to standard laboratory methods, often used in the study of memory at any age. Last two
From the book General Psychology author Dmitrieva N Yu8. Associative psychology In the process of formation of psychology, the associationist approach to perception began to prevail. Associative psychology is one of the main directions in psychology of the 17th–19th centuries. The main explanatory principle of mental life was the concept
From the book All the best that money can't buy. A world without politics, poverty and wars by Fresco Jacques by Andrew Newberg From the book The Mystery of God and the Science of the Brain [Neurobiology of Faith and Religious Experience] by Andrew Newberg From the book The Mystery of God and the Science of the Brain [Neurobiology of Faith and Religious Experience] by Andrew NewbergAssociative memory is distributed memory that learns from associations, much like the brains of living things. In information technology, memory is accessed not by address, but by content. A model that implements associative memory must recognize the required image and retrieve it.
Unlike conventional machine memory, in which the user specifies a memory address and the RAM returns a word of data stored at that address, the AM is designed in such a way that the user specifies a data word, and the AM searches the entire memory for it to find out if it is stored where something in it. If a data word is found, the AP returns a list of one or more storage addresses where the word was found (and on some architectures, also returns the data word itself, or other associated pieces of data). Thus, the AP is a hardware implementation of what in programming terms would be called an associative array.
Autoassociative memory
Heteroassociative memory
Describe the two phases in the work of associative memory
- key image, 
-memorized vector of images, 
-number of images (capacity). The key image not only acts as a stimulus that determines the location of the memorized image, but also contains the key for retrieving it. Recovery phase. Corresponds to the process of retrieving a stored image in response to a noisy or corrupted version of a key being presented to the network.
Give a definition of the pattern recognition process
Describe the two types of pattern recognition machines.
The system consists of two parts: a feature extraction network (unsupervised) and a classification network (supervised). Image – a set of 
observations, each observation can be considered a point 
in -dimensional space of observations (data). Feature extraction is described using a transformation that translates to an intermediate point 
in -dimensional feature space 
. This transformation can be considered as a dimensionality reduction operation (data compression), which simplifies the classification task. Classification is a transformation that maps an intermediate point to one of the classes 
-dimensional space of solutions ( - number of distinguished classes).
2nd type of machine.
The system is designed as a single multilayer feedforward network using one of the supervised learning algorithms. In this approach, the task of feature extraction is performed by the computing nodes of the hidden layer of the network.
Describe a method for solving the system identification problem.
Describes the relationship between input and output in an unknown system with multiple inputs and outputs without memory (time invariant system). Then the set of labeled examples can be used to train a neural network representing a model of this system. Let 
- output of the neural network corresponding to the input vector 
. Error signal ( 
=
(desired response) - (network output)) is used to adjust the free parameters of the network in order to minimize the mean square error 
Describe the method for constructing an inverse system
generates a response as a vector. The inverse system can be described as follows: 
vector function 
-inverse. Based on many labeled examples ( 
) you can build a neural network that approximates the inverse function using the circuit: 
() is the desired response, () is the input signal (vectors , - have swapped places). Vector error signal 
is equal to the difference between the desired vector and the actual output of the neural network, obtained in response to the disturbance. Here, the error signal vector is used to minimize the sum of squared differences between the outputs of the unknown inverse system and the neural network in a static sense (i.e., calculated on the entire set of training examples).
Provide a block diagram of a feedback control system
This system uses a single feedback that covers the entire control object. Thus, the output of the control object is subtracted from the reference signal () received from an external source. The error signal (e) obtained in this way is fed to the neurocontroller to configure free parameters. The main task of the controller is to maintain such an input vector of the object for which the output signal (y) would correspond to the reference value (d). In other words, the controller's task is to invert the input-output mapping of the control object.
Describe the operations of logical sum and logical product on fuzzy sets
, which is equal to 1 if the element belongs to set A, or equal to 0 otherwise. In fuzzy systems, an element can partially belong to any set. The degree of membership in the set A, which is a generalization of the characteristic function, is called the membership function, and 
, And 
means that x does not belong to the set A, and 
- full ownership. The specific value of the membership function is called the degree or membership coefficient. Logical sum operation:
Let 
- the smallest fuzzy subset that includes both 
so and 
with membership function:
Operation of logical product on fuzzy sets:
Let 
- the largest fuzzy subset that is contained simultaneously in and in , then the membership function has the form:
Describe the operations of set negation and set normalization for fuzzy sets
Let 
- all the multitude that is not 
, then an element belonging to the set is determined according to the function:
Normalization of fuzzy sets:
SUPREMUM: Sup is the supremum (the maximum membership value present in the set).
NORMALIZATION: a fuzzy set is normal if the supremum of the set is equal to one. To normalize, the affiliations of the elements are reread:
M"a(x) = Ma(x)/(Sup Ma(x))
Describe the operation of concentration and stretching for fuzzy sets
Blur operation: 
Define a linguistic variable
Mathematical definition of a linguistic variable: 
, where is the name of the variable; 
- a set of names of linguistic values of a variable, each of which is a fuzzy variable on the set 
; 
- syntactic rule for the formation of value names; 
a semantic rule for associating each value with its concept.
Describe the algebraic product operation for fuzzy sets
(aggregation of premises).
Describe the Jäger measure, which characterizes the degree of vagueness of sets
,
number of elements in , 
distance between sets and in the metric 
(which is equal to 1 or 2). The Hamming metric corresponds to the value 
Describe the Euclidean metric characterizing the measure of fuzziness of a set
called the Euclidean metric: 
.
Describe the entropy measure of fuzziness of the Cosco set
Cardinal number of a set 
the sum of the membership coefficients of all elements of this set, i.e. 
.
Describe the Mamdani-Zadeh fuzzy inference system
many fuzzy rules used;
a database containing descriptions of membership functions;
an inference and aggregation mechanism that is formed by the applied rules of implication.
To ensure the interaction of these two types, a fuzzy system is introduced with a so-called phasifier (converter of input data sets into a fuzzy set) at the input and a defasifier (converter of fuzzy sets into a specific value of the output variable) at the output.
The output signal of the output module can be in the form of fuzzy sets that determine the range of change of the output variable. The defasifier converts this range into one specific value, which is taken as the output of the entire system.
The Mamdani-Zadeh inference model contains the following operators: 
Figure 1. Example of the Mamdani-Zadeh inference system
In Fig. 1 shows the method of aggregation with two input variables.
Describe the fuzzifier
Describe the concept of membership function
Membership coefficient is a value from the range that characterizes the degree of membership of an element to a fuzzy set.
A real number taking a value in the range (0,1), with 1 meaning 100% (unconditional) membership of a in the set, and 0 - unconditional absence in . Values between 0 and 1 characterize unclearly included elements.
The mapping from a set of elements to a set of values forms a membership function.
The function can be defined explicitly as, for example, an algebraic expression or tabulated (discretely) as an array of pairs
Describe the generalized Gaussian membership function
and width parameter 
has the form: 
There is also a generalized Gaussian function: 
form parameter. 
Rice 3. Graph of the generalized Gaussian function forc=1,
The generalized Gaussian function can also be in rational form: 
.
Describe the concept of defuzzification of a fuzzy set
Describe defuzzification relative to mean center
Where 
center 
-th single membership function participating in the final aggregated function.
Describe defuzzification relative to the center of the region
or in discrete form 
.
Give a flowchart of how a genetic algorithm works.
Describe the concepts of integer and real coding.
As a rule, the numerical parameters of the solution are encoded in the chromosome. For this purpose, it is possible to use integer and real coding.
Integer coding.
In a classical genetic algorithm, a chromosome is a bit string in which the parameters for solving a given problem are encoded.
Real coding.
It is often more convenient to encode a real number rather than an integer in a gene. This eliminates the encoding and decoding operations used in integer coding and increases the accuracy of the solution.
Describe selection methods.
Roulette selection. In this selection option, the probability of the i-th individual to take part in the crossing pi is proportional to the value of its fitness fi and is equal to .
The process of selecting individuals for crossing is reminiscent of a game of roulette.
The roulette circle is divided into sectors, and the area of the i-th sector is proportional to the value of pi. After this, the roulette is “spun” n times, where n is the population size, and the individual selected for crossing is determined by the sector where the roulette stops.
Selection by truncation. When selecting by truncation, after calculating fitness values, Ln best individuals are selected for crossing, where L is the “cut-off threshold”, 0
As a rule, choose L in the range from 0.3 to 0.7.
Tournament selection. In the case of using tournament selection for crossing, as in roulette selection, n individuals are selected.
To do this, t individuals are randomly selected from the population, and the fittest of them is allowed to cross. They say that a tournament is formed from t individuals, t is the size of the tournament. This operation is repeated n times.
The larger the t value, the greater the selection pressure. The variant of tournament selection when t = 2 is called a binary tournament. Typical tournament size values are t = 2, 3, 4, 5.
28. Describe the principle of operation of single-point, two-point and homogeneous crossover operators for integer coding.
For integer encoding, the 1-point, 2-point, and uniform crossover operators are often used.
1-point crossover works similarly to the chromosome crossover operation when crossing biological organisms. To do this, an arbitrary break point is selected and parts of the parent chromosomes are exchanged to create offspring.
For the 2-point crossover operator, 2 random breakpoints are selected, after which the parent chromosomes exchange the regions between the breakpoints to create offspring. Note that for the 2-point crossover operator, the beginning and end of the chromosome are considered “glued”, as a result of which one of the breakpoints may fall into the beginning/end of the chromosomes, and in this case the result of the 2-point crossing over will coincide with the result of the 1-point crossover crossing over.
When using the homogeneous crossing over operator, the ranks of the parent chromosomes are inherited independently of each other. To do this, determine the probability p0 that the i-th digit of the chromosome of the 1st parent will go to the first descendant, and that of the 2nd parent will go to the second descendant. The probability of the opposite event is (1 – p0). Each rank of the parent chromosomes is “played out” in accordance with the p0 value between the chromosomes of the descendants. In most cases, the probability of both events is the same, i.e. p0 = 0.5.
29. Describe the operating principle of a two-point crossover for real-valued encoding.
The 2-point crossing over for real encoding is generally similar to the 2-point crossing over for integer encoding. The difference is that the breakpoint cannot be chosen “within” the gene, but must fall between genes
30. Describe the concept of the destructive ability of a crossover.
Crossing over operators are characterized by the ability to destroy parental chromosomes.
Crossing over for integer coding is considered more destructive if, as a result of its application, the Hamming distance between the resulting chromosomes of the offspring and the chromosomes of the parents is large.
In other words, the ability of an integer crossover to disrupt depends on how much it “mixes” (recombines) the contents of the parent chromosomes. Thus, 1-point crossing over is considered a weakly destructive operator, and a uniform crossing over in most cases is a highly destructive operator. Accordingly, 2-point crossing over in terms of destructive ability occupies an intermediate position in relation to 1-point and homogeneous crossing over operators.
In the case of crossover for real coding, the ability to break is determined by how large the distance in search space is between the points corresponding to the parent and offspring chromosomes. Thus, the destructive effect of 2 point crossing over depends on the content of the parental chromosomes. The destructive ability of arithmetic crossing over depends on the value of the parameter l, for example, for l >> 1 and l >> 0, the destructive ability will be low. For BLX-a crossing over, the destructive ability depends both on the value of a and on the difference in the values of the corresponding genes of the parent individuals.
Let us note that along with the ability to destroy, they also talk about the ability to create (creation, construction) new individuals by crossing over. This emphasizes that, by destroying the chromosomes of parental individuals, crossing over can create completely new chromosomes that were not previously encountered in the process of evolutionary search.
31. Describe the canonical genetic algorithm.
The canonical genetic algorithm was developed by John Holland and described in his book Adaptation in Natural and Artificial Systems, 1975. Represents one of the basic models of evolutionary search, studied in detail in the 70-80s of the 20th century.
The canonical GA has the following characteristics:
Integer coding;
All chromosomes in a population are the same length;
Constant population size;
Roulette selection;
One-point crossover operator;
Bit mutation;
A new generation is formed only from descendant individuals (generation gap T = 1).
32. What models of knowledge representation do you know?
The most common models of knowledge representation in expert systems are:
model of knowledge representation using first-order predicate logic;
product model;
frame model;
model of knowledge representation in the form of a semantic network;
knowledge representation model in the form of a bulletin board;
model of knowledge representation in the form of a scenario;
model of knowledge representation based on fuzzy logic;
neural network model of knowledge representation.
The logical model of knowledge representation is based on predicate logic. A predicate, or logical function, is a function of any number of arguments that takes a true or false value. Function arguments – values from an arbitrary, finite or infinite set 
, called the subject area. Predicate from 
-arguments are called -local predicates. The knowledge representation model uses first-order predicate logic, which is what Prolog is based on.
34. What does a production system consist of?
A production system is a knowledge processing system that uses knowledge representations by production rules. Production rules are expressions like “If (condition) then (action).” “Condition” is a sample sentence by which a search is carried out in the knowledge base; “action” – the action performed when the search is successful. The conclusion on such a knowledge base can be direct (from data to searching for a goal) and reverse (from a goal to confirm it - to data). Data are the initial facts stored in the fact base, on the basis of which the inference engine or rule interpreter is launched, enumerating the rules from the production knowledge base.
The production system includes a rule base, a database and a rules interpreter. The rule base is a memory area that contains a knowledge base - a body of knowledge presented in the form of rules of the form IF ... THEN; A database is an area of memory containing actual data (facts). The interpreter is the inference mechanism; it is the component of the system that generates a conclusion using a rule base and a database.
35. Describe the model for representing knowledge in the form of frames
In a frame system, the unit of knowledge representation is an object called a frame. A frame is a form of representation of a situation that can be described by a certain set of concepts and entities. The frame is given a name as an identifier. This name must be unique in the entire frame system. A frame has a specific internal structure consisting of many elements called slots, which are also named. Each slot, in turn, is represented by a specific data structure. Sometimes a slot includes a component called a facet, which specifies a range or list of its possible values. The facet also specifies the slot filler boundary values (for example, the maximum number of siblings allowed
36. How is knowledge represented in the semantic network?
A semantic network represents knowledge in the form of a graph, the nodes of which correspond to facts or concepts, and the arcs correspond to relationships between concepts. A graph is a set of vertices and a set of arcs connecting some pairs of vertices. The labeled graph for each vertex contains descriptors (labels), thanks to which the vertices of the graph differ from each other. For a state space graph, descriptors identify states in the process of solving a problem. Arc labels in semantic networks are used to define named relationships.
37. Describe the architecture of expert systems
A group of experts or other source of expertise ensures that facts, observations, and ways to analyze situations are loaded into the knowledge base. The user queries the system about specific problems through an interface that allows communication using common expressions.
The information contained in the knowledge base is processed by an inference engine, which uses empirical associations or "IF...THEN" rules to generate and test possible solutions. The user interface transmits the results obtained to the operator in an accessible form.
Powerful intelligent systems have a natural language interface that allows you to ask questions and receive answers in plain English or Russian. In the case of conventional intelligent systems, the user is presented with a less sophisticated, but nevertheless “friendly” interface.
38. Describe the functions of the output machine (mechanism)
The main thing in an ES is a mechanism that searches the knowledge base according to the rules of rational logic to obtain solutions. This mechanism, called the inference engine, is activated upon receiving a user request and performs the following tasks:
compares the information contained in the user's request with the knowledge base information;
looks for specific goals or causal connections;
evaluates the relative certainty of facts based on the corresponding confidence coefficients associated with each fact.
39. Provide a block diagram describing the stages of technology for creating expert systems
At the identification stage, tasks that need to be solved are determined, development goals, resources, experts and categories of users are identified.
At the knowledge acquisition stage, there are three strategies: knowledge acquisition, knowledge extraction and knowledge discovery. The acquisition of knowledge is understood as a method of automated filling of the knowledge base through a dialogue between an expert and a special program. Knowledge extraction is the procedure for interaction between a knowledge engineer and a source of knowledge (an expert, specialized literature, etc.) without the use of computer technology. The term knowledge discovery is associated with the creation of computer systems that implement methods for automatically obtaining knowledge. Now this direction is the most promising. In this case, it is assumed that the system itself will be able to reveal the laws of the subject area and formulate the necessary knowledge based on the available empirical material.
At the conceptualization stage, an analysis of the problem area is carried out, the concepts used and their relationships are identified, and methods for solving problems are determined.
The formalization stage determines ways of representing all types of knowledge, formalizes basic concepts, determines ways of interpreting knowledge, and models the operation of the system. At this stage, the adequacy of the system of fixed concepts, solution methods, means of representing and manipulating knowledge is assessed.
At the execution stage, the system knowledge base is filled. At the testing stage, the expert (and knowledge engineer) interactively, using dialog and explanatory tools, checks the competence of the ES. The testing process continues until the expert decides that the system has achieved the required level of competence.
At the trial operation stage, the suitability of the ES for end users is checked. Based on the results of this stage, as well as the testing stage, significant modification of the ES may be required.
The process of creating an ES is not limited to following the strict sequence of the steps listed above. During development, you have to repeatedly return to earlier stages and revise the decisions made there.
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