Types of dynamic RAM

As already noted, the information in the cell dynamic RAM represented as the presence or absence of charge on the capacitor. Memory cell diagram YAP A dynamic memory on one MOS transistor with an induced p-channel is shown in Fig. 6.6 (highlighted dotted line). The diagram also shows the common elements for n-cells of one column. The main advantage of this scheme is its small footprint. Storage capacitor C 1 has a MIS structure and is manufactured in a single technological cycle. The value of its capacitance is hundredths of picofarads. Capacitor C 1 stores information charge. Transistor VT 1 acts as a switch that transfers the capacitor charge to the bit data bus SD when reading, or charging the capacitor when writing. In storage mode, a logical one potential must be present on the address line, under the influence of which the transistor VT 1 will be closed ( U ziVT 1 ?0) and capacitor C 1 disconnected from the data bus SD. The capacitor is connected to the data bus by a logical zero on the line. At the same time, the transistor VT 1 voltage applied U zi.VT 1 <0, что приводит к его открыванию.

Rice. 6.6. Schematic diagram of a dynamic RAM cell with elements of a write and a read amplifier.

Since the data bus SD unites all memory cells of a given column, then it is characterized by a large length and its own capacity is essential. Therefore, when opening the transistor VT 1 the data bus potential changes slightly. So that the steady potential at SD uniquely identify with the voltage level of logical zero or logical one, a transistor-based amplifier is used VT 2 and resistor R. Immediately before reading, the capacity of the data bus is recharged by connecting it to a power source through a transistor VT 4. This is done to fix the potential of the data bus. When reading information, a redistribution of the capacitor charge and data bus charge occurs, resulting in the information stored on the capacitor WITH 1, is destroyed. Therefore, in the reading cycle it is necessary to restore (regenerate) the charge of the capacitor. For these purposes, as well as for writing new values ​​to a memory cell, transistors are used VT 3 and VT 4, which connect the data bus either to a power supply or to zero common potential. To write a logical unit to a memory cell, it is necessary to open transistor VT4 with a zero value of the control signal “” and connect a power source to the data bus. To record a logical zero, it is necessary to open transistor VT3 with zero potential at the input ““. Simultaneous supply of logical zeros to the “” and “” inputs is not allowed, as this will cause a short circuit of the power supply to the common ground wire.

In Fig. Figure 6.7 shows an example of the structure of a 64kbit dynamic RAM chip. The data in this memory chip is represented as 64k individual bits, i.e. memory format 64k?1. Input and output are carried out separately, for which a pair of outputs is provided D.I.(input) and DO(exit). There are eight contacts for entering the address A 0 — A 7. Addressing 64k memory cells is carried out by sixteen-bit addresses A 0 — A 15. And first at the entrances A 0-A 7 eight least significant digits are supplied A 0 – A 7 addresses, and then the eight most significant digits A 8 – A 15. The lower eight bits of the address are latched into the row address register by applying a signal (row fetch signal). The eight most significant bits of the address are latched into the column address register by applying a signal (column fetch signal). This mode of address code transmission is called time multiplexed. Multiplexing allows you to reduce the number of pins on the chip. The memory cells are arranged in a matrix of 128 rows and 512 columns. The string decoder generates an address signal for sampling memory cells i-th line, i.e. one of 128 lines is selected. A row access causes 512 memory cells to be connected via the corresponding data bit lines SD this row to the sense amplifiers (one per column). In this case, the storage capacitors of all memory cells of the selected row are automatically recharged to the initial level due to the transmission of an amplified signal through the feedback circuit. This process is called memory regeneration. The column decoder selects one of 512 sense amplifiers. The bit selected in read mode is output to the line DO. If a recording signal is active simultaneously with a signal at a preset signal, then the bit from the input D.I. will be written to the selected memory cell, and the output DO The microcircuit remains in the off state during the entire write cycle.

Rice. 6.7. The structure of a dynamic RAM chip.

In Fig. Figure 6.8 shows timing diagrams explaining the operation of dynamic RAM. In read mode (Fig. 6.8, A) eight low-order bits are supplied to the address inputs of the microcircuit A 0 – A 7 addresses, after which the signal is generated, and a matrix row is selected in accordance with the received address. All memory cells of the selected row have their capacitor charge regenerated. Next, the eight most significant bits of the address are supplied to the address inputs of the microcircuit, after which the signal is generated. This signal selects the desired memory cell from the selected row and the read bit of information is sent to the output of the microcircuit DO. In read mode, the time interval between the signal and the appearance of data at the output DO called sampling time t in.

Rice. 6.8.Time diagram of dynamic RAM operation.

In recording mode (Fig. 6.8, b) during the recording cycle t cz the time interval between the appearance of the signal and the end of the signal is taken. At the moment the signal appears, the recorded data must already be arriving at the input D.I.. The signal is usually produced before the signal.

For each type of dynamic RAM chip, the reference books provide time parameters that regulate the duration of the control signals supplied to the chip, as well as the order of their mutual succession.

The charge on the dynamic RAM capacitor decreases over time due to leakage, so in order to preserve the memory contents, the regeneration process of each memory cell must occur after a certain time. Therefore, to prevent the storage capacitors from discharging, it is necessary to access each row of the matrix after a certain time. In normal RAM operation mode, this condition is not met, since some cells are accessed frequently, while others are accessed very rarely. Therefore, a special unit responsible for memory regeneration is required. This block should, in the absence of access to RAM from external devices, cyclically form at the address inputs A 0-A 6 the values ​​of all possible addresses, accompanying each of them with a control signal, i.e. perform cyclic access to all 128 rows of the matrix of memory cells. Regeneration must also be carried out at those moments in time when the RAM is used by devices, suspending the interaction of the RAM with these devices during regeneration, i.e. by putting these devices into standby mode.

From the above it follows that the use of dynamic RAM requires a rather complex control circuit. If we take into account that access to RAM by the devices with which it works and access by the regeneration circuit do not depend on each other, therefore, they can occur simultaneously, then a circuit is needed to ensure the ordering of these accesses. For these purposes, there are circuits that control the operation of dynamic RAM. These are so-called dynamic RAM controllers implemented on a single chip. Their use can significantly simplify the construction of memory on dynamic RAM.

The leader in the production of dynamic RAM chips today is Samsung. The capacity of one DRAM chip reaches 128 MB or more. In addition, this company offers a number of advanced ideas to ensure maximum performance. For example, read and write operations are performed twice in one clock cycle - on the rising and falling edges of the clock pulse. Mitsubishi has proposed the concept of embedding a small static cache memory (Cashed DRAM) into dynamic memory chips, which stores the most frequently requested data.

Dynamic RAM

Dynamic Random Access Memory (DRAM) is a volatile semiconductor memory with random access. At the moment, this is the main type of RAM used in modern personal computers and provides the best price-quality ratio compared to other types of RAM. However, demands for speed, power consumption and reliability of RAM are constantly increasing, and dynamic RAM is already struggling to meet modern needs, so we can expect competing types of RAM, such as magnetoresistive RAM, to become commercially available in the coming years.

1. Dynamic random access memory device.

Dynamic Random Access Memory (DRAM) is a volatile random access memory, each cell of which consists of one capacitor and several transistors. The capacitor stores one bit of data, and the transistors act as switches that hold the charge in the capacitor and allow access to the capacitor when reading and writing data.

However, the transistors and capacitor are not ideal, and in practice the charge from the capacitor runs out quite quickly. Therefore, periodically, several tens of times per second, it is necessary to recharge the capacitor. In addition, the process of reading data from dynamic memory is destructive, that is, when reading, the capacitor is discharged, and it is necessary to recharge it again so as not to permanently lose the data stored in the memory cell.

In practice, there are different ways to implement dynamic memory. A simplified block diagram of one of the implementation methods is shown in Figure 1.

As can be seen from the figure, the main memory block is a memory matrix, consisting of many cells, each of which stores 1 bit of information.

Each cell consists of one capacitor (C) and three transistors. Transistor VT1 allows or prohibits writing new data or cell regeneration. Transistor VT3 acts as a key that keeps the capacitor from discharging and allows or prohibits reading data from the memory cell. Transistor VT2 is used to read data from the capacitor. If there is a charge on the capacitor, then the transistor VT2 is open, and the current will flow along line AB, respectively, there will be no current at the output Q1, which means that the cell stores a bit of information with a zero value. If there is no charge on the capacitor, then capacitor VT2 is closed, and the current will flow through line AE, accordingly, there will be current at the output Q1, which means that the cell stores a bit of information with the value “one”.

The charge in the capacitor, used to maintain transistor VT2 in the open state while current passes through it, is quickly consumed, so when reading data from the cell, it is necessary to regenerate the capacitor charge.

For dynamic memory to work, voltage must always be supplied to the matrix; in the diagram it is indicated as Up. With the help of resistors R, the supply voltage Up is evenly distributed between all columns of the matrix.

The memory also includes a memory bus controller, which receives commands, addresses and data from external devices and relays them to internal memory blocks.

Commands are transmitted to the control unit, which organizes the operation of the remaining blocks and periodic regeneration of memory cells.

The address is converted into two components - a row address and a column address, and is transmitted to the appropriate decoders.

The line address decoder determines which line needs to be read or written from and outputs a voltage to that line.

The column address decoder, when reading data, determines which of the read data bits have been requested and should be issued to the memory bus. When writing data, the decoder determines which columns to send write commands to.

The data processing unit determines what data needs to be written to which memory cell, and produces the corresponding data bits to be written to these cells.

Regeneration blocks define:

• when data is being read and it is necessary to regenerate the cell from which the data was read;
• when data is being written, and, therefore, there is no need to regenerate the cell.

The data buffer stores the entire read row of the matrix, since when reading the entire row is always read, it then allows you to select the required data bits from the read row.

Let's consider the principle of operation of dynamic memory using the example of the block diagram shown in Figure 1. We will consider working with the first cell (M11). The operation of the remaining memory cells is completely identical.

1.1. Dynamic memory performance at rest.

And so, the first thing we will consider is this state of rest, when there are no accesses to memory, and it is not at the stage of data regeneration.

DRAM is a volatile memory, so it can only be accessed when power is supplied. In the diagram, the power supplied to the board is indicated as Up. The supplied power is distributed among all columns of the memory matrix using transistors R.

If the memory is idle (no commands come from the memory bus controller), then the row address decoder does not output a signal to any row line (S1-Sn) of the memory matrix. Accordingly, transistors VT1 and VT3 of memory cells M11 are closed, as well as similar transistors of all other memory cells.

Consequently, the current from the supplied power flows through line AE for the first column and similarly for all other columns of the memory matrix. Then it goes to outputs Q1-Qm, at which a “high” voltage level is set, corresponding to the logical value “1”. But since there are no commands from the control unit, the “Data Buffer” ignores the received signals.

Here it becomes clear why transistor VT3 is needed. It protects the capacitor from discharge when a given memory cell is not accessed.

The current through the AE line also flows to the “Regeneration Block 1”, namely, to the lower input of element L3 (logical “AND”), that is, a logical one is supplied to the lower input of element L3.

Let's consider how the regeneration unit will work in this case.

Since there are no signals from the memory controller, the input of element L1 (logical “NOT”) will be logical zero, and, accordingly, the output will be logical “1”. Thus, at the upper input of element L3 (logical “AND”) there will be a logical one.

Having two logical units at the inputs of element L3 (logical “AND”), we also get a logical one at the output.

The output of element L2 (logical “AND”) will be logical zero, since there is no voltage at both of its inputs, since there are no commands or data from the memory controller.

As a result, at the inputs of element L4 (logical “OR-NOT”) there will be a logical zero and a logical one, and, accordingly, at its output there will be a logical zero, that is, there will be no voltage. Since there is no voltage, not a single capacitor in the first column of the memory matrix will be recharged. Although, even if voltage were present, recharging would still be impossible, since the charging transistors (a portion of cell M11 is VT1) would be closed, because no voltage is supplied to any row of the memory matrix (S1-Sn).

Exactly the same situation will happen with all columns of the memory matrix.

Thus, when the memory is inactive, the capacitors are not recharged and store the charge (and, accordingly, the bit of data) that they had since the last recharge. However, this cannot continue for long, since due to self-discharge, the capacitor will discharge after a few tens of milliseconds, and the data will be lost. Therefore, it is necessary to constantly regenerate memory.

1.2. Dynamic memory operation when reading data and regenerating.

We will consider the principle of reading data from dynamic memory using the example of reading data from memory cell M11:

1. The processor requests a piece of data (the size depends on the processor bit size; for a 32-bit processor, the minimum unit of exchange is usually 32 bits) and issues its address.

2. The memory bus controller converts the address into row number and column number and outputs the row number to the row address decoder. The row address decoder outputs a signal to the corresponding row of the memory matrices. We agreed that in the example we will read data from the first memory cell. Therefore, the row address decoder will apply voltage to the first row (S1).

3. The voltage applied to row S1 will open transistors VT1 and VT3 of the first memory cell and the corresponding transistors of all other cells of the first row.

4. Further operation of the memory depends on the presence or absence of charge on the capacitor. Let us consider separately two cases when there is a charge on the capacitor of cell M11 and when there is not.

4.1. First, let's consider the case when there is a charge in the capacitor (the memory cell contains a bit with the value zero):

Since there is a charge on capacitor C of memory cell M11, transistor VT2 will be open, and, accordingly, the current created by the input voltage Up will flow along line AB. As a result, there will be no current column at the output of Q1. This means that zero has been read from memory cell M11. The corresponding information about the bit read from the first column will be written to the “Data Buffer”.

To maintain transistor VT2 in the open state and current flow through line AB, the charge of capacitor C is consumed. As a result, the capacitor will discharge very quickly if it is not regenerated.

Since there is no current at output Q1, it will not flow into “Regeneration Unit 1”, and, accordingly, at the lower input of element L3 (logical “AND”) there will be a logical zero.

Since we are considering the case of reading data, the V1 write signal and D1 write data will not be supplied to “Regeneration Block 1”. The corresponding signals D1-Dm and V1-Vm will also not be supplied to the remaining regeneration blocks.

As a result, the input of element L1 (logical “NOT”) will be logical “0”, and the output will be logical “1”, so the inputs of element L3 (logical “AND”) will be logical “0” and logical “1”. This means that the output of this element will be logical “0”.

The output of logic element L2 (logical “AND”) will be logical zero, since there is no voltage at both of its inputs, since there are no write commands and no data to write from the memory bus controller.

Having a logical “0” at both inputs of element L4 (logical “OR-NOT”), at its output we will have a logical “1”, that is, the regeneration unit will supply the recharging current for capacitor C. Since the recharging transistor VT1 of memory cell M11 is open, then the charging current will freely pass into capacitor C. The remaining memory cells of the first column have a closed charging capacitor, and, therefore, their capacitors will not be recharged.

4.2. Now consider the case when there is no charge in the capacitor (the memory cell stores a bit with the value “1”):

The current created by the input voltage Up will flow along line AE, since transistor VT2 will be closed. Consequently, there will be a current at the input Q1 of the “Data Buffer”, which means a unit has been read from the memory cell. Information about the read bit from the first column will be written to the “Data Buffer”.

Since there was no charge in the capacitor, there is no need to recharge it. Therefore, no current should flow from the regeneration unit.

Since there is current at output Q1, it also goes to the “Regeneration Block”. Consequently, a logical one is supplied to the lower input of element L3 (logical “AND”).

Since we are considering the case of reading data, the V1 write signal and D1 write data will not be supplied to “Regeneration Block 1”. Also, the corresponding signals D1-Dm and V1-Vm will not be supplied to the remaining regeneration blocks.

Consequently, the input of element L1 (logical “NOT”) will be logical zero, and the output will be logical “1”. Thus, there will be two logical ones at the inputs of element L3 (logical “AND”). As a result, the output will also be a logical one.

The output of logic element L2 (logical “AND”) will be logical zero, since there is no voltage at both of its inputs, since there are no write commands or data to write from the memory controller.

As a result, at the inputs of element L4 (logical “OR-NOT”) there will be a logical zero and a logical one, and, accordingly, at its output there will be a logical zero, that is, there will be no voltage. Since there is no voltage, none of the capacitors in the first column of the memory matrix will be recharged.

5. In parallel with reading and regenerating data from the first column, data from the remaining columns is read using the same algorithm. As a result, the value of all memory cells of the first row will be written to the data buffer.

6. Column numbers for reading are issued from the memory controller to the column address decoder. In one clock cycle, numbers are read from several columns at once. The number of columns to read is determined by the bit size of the processor and the way it interacts with memory. For 32-bit processors, the minimum portion is to read data from 32 columns.

7. From the column address decoder, the column numbers are transferred to the “Data Buffer”, from where the corresponding data is read and transferred to the processor.

This completes the data reading cycle. As you noticed, when reading data, values ​​are read from the entire data memory line at once, and then the required data is selected from it in the “Data Buffer”. Therefore, the minimum portion of reading data from dynamic RAM is a string.

When reading data, it is also regenerated at the same time. However, not all RAM data is constantly needed for work, so access to some memory cells may be very rare. To ensure that the data in such cells is not lost, they must be read forcibly, without waiting until the processor needs them.

Therefore, the “Control Unit” with a certain frequency, during moments of memory idle time or between accesses to the memory of the processor (or other devices), regenerates data in all memory cells.

1.3. Dynamic memory operation when writing data.

We will consider the principle of writing data to dynamic memory using the example of writing data to memory cell M11:

1. The memory bus controller receives a command to write data, data and the address where this data should be written.

2. The memory bus controller converts the address into two components - row number and column numbers, and transmits the resulting components to the “Row Address Decoder” and the “Column Address Decoder”. And the data is transferred to the “Data Processing Unit”.

3. The row address decoder outputs a signal to the corresponding row of the memory matrix. We agreed that in the example we will write data to the first memory cell. Therefore, the row address decoder will apply voltage to the first row (S1).

4. Simultaneously, V signals are issued from the “Column Address Decoder” into the columns corresponding to the received address. The same columns receive D signals from the “Data Processing Unit”, the level of which is determined by the value of the bits of the word being written.

5. The voltage applied to row S1 will open capacitors VT1 and VT3 of the first memory cell and the corresponding capacitors of all other cells of the first row.

6. If cell M11 stores a bit with the value “0” (there is a charge in the capacitor), then the current created by the input voltage Up will flow along line AB, otherwise – along line AE. But this is not important to us, since data is written to cell M11, not read, so the data buffer will ignore the value read from the cell. And the output of element L3 of “Regeneration Block 1” will always be logical zero, since a signal (V1) comes from the column decoder to write data to the first column.

As a result, the input of element L1 will be a logical one, and the output will be a logical zero. Accordingly, at the upper input of the L3 element we always have a logical zero, which means that regardless of the values ​​​​at the lower input, the output of the L3 element will be a logical zero.

At the lower input of the L2 element there will be a logical one, since the V1 signal is issued from the column address decoder, and at the upper input there will be either a zero or a one, depending on the value of the bit of the information being written.

If the bit has the value “1”, then the upper input of the L2 element will be “1”. Having two ones at the input, we will also get a logical one at the output. Accordingly, a logical “1” and a logical “0” will be received at the inputs of element L4. As a result, the output will be logical “0”, that is, there will be no current, and, accordingly, capacitor C will not be charged. If capacitor C previously contained a charge, then after a few microseconds it will discharge, passing current through line AB. Thus, a data bit “1” will be written to capacitor C, corresponding to the discharged state of the capacitor.

If the bit has the value “0”, then the upper input of the L2 element will be “0”. Having a logical zero at the upper input and a logical one at the lower input, we obtain a logical zero at the output of element L2. As a result, at the upper and lower inputs of element L4 we have logical zeros, which means that the output of element L4 will be a logical one, that is, the capacitor charging current will flow. Thus, a data bit “0” will be written to capacitor C, corresponding to the charged state of the capacitor.

Similarly, data will be written to other columns of the memory matrix. In those columns in which data writing is not required, data will be read from the memory cell and regenerated. In this case, no data will be written to the memory buffer.

Writing data to all required cells of a row of the memory matrix and reading with regeneration from the remaining cells of the row are performed in parallel.

The memory block diagram shown in Figure 1 and the described operating principle correspond to one of the simplest organizations of dynamic memory. In practice, such memory has not been used for a long time. Over time, it underwent a number of changes that allowed it to work much faster. Let's take a look at these improvements.

2. Stages of modernization of dynamic random access memory.

All improvements in the operation of dynamic memory were aimed at increasing the speed of memory, since the speed of RAM has been one of the factors limiting the growth of computer performance throughout the history of computing. If we look at the history of computers, we can see that every breakthrough in the field of organizing RAM led to a sharp jump in computer performance.

Naturally, the speed of memory increased due to an increase in clock frequency and improvement in the production process. This was a natural process that led to a smooth increase in work speed. But we are more interested in changes in the fundamental structure of memory, which led to the emergence of new types of memory. These are the ones I will talk about in this chapter.

2.1. PM DRAM.

One of the first types of RAM used in personal computers was simple dynamic random access memory (PM DRAM - Page Mode DRAM), the principle of which is described above. PM DRAM was used until the mid-90s.

However, its speed was sorely lacking, so it was replaced in 1995 by FPM DRAM memory.

2.2. FPM DRAM.

FPM DRAM (Fast Page Mode DRAM) – fast page memory. Its main difference from FP DRAM was its support for stored addresses. That is, if a new word read from memory was in the same line as the previous word, then access to the memory matrix was not required, and data was sampled from the “Data Buffer” (see Figure 1) by column numbers. This made it possible to significantly reduce the reading time when reading data arrays from memory.

However, writing data to memory was carried out in exactly the same way as in PM DRAM. And the read data was not always located on one line. As a result, productivity gains were highly dependent on the type of programs the computer was working with. The increase could be significant, or there could be a slowdown in work due to additional overhead costs for analyzing the line number of the previous reading operation.

The next type of memory, replacing FPM DRAM, appeared a year later (in 1996) and was called EDO-DRAM.

2.3. EDO-DRAM.

EDO-DRAM (Extended Data Out DRAM) – dynamic memory with improved output. In this type of memory, the address of the next word to be read was transmitted before the read of the memory data line was completed, that is, before the data read from the memory was transferred to the processor.

It became possible to start reading a new word of data before finishing reading the previous one thanks to the introduction of so-called registers - latches, which saved the last word read even after reading or writing the next word began.

Combining also the innovations of FPM RAM, the new type of memory gave a peak performance increase reaching 15-20%.

However, progress did not stand still; the clock speeds of processors, the system bus and, of course, memory increased. As clock speeds increased, it became more and more difficult to achieve stable operation of EDO-DRAM memory, since due to unexpected delays, reading a new data word could begin before the previous data word was stored using register latches.

As a result, EDO-DRAM was replaced by SDRAM memory.

2.4. SDRAM.

SDRAM (Synchronous DRAM) – synchronous dynamic random access memory. As the name suggests, the memory worked synchronously, synchronously with the memory controller, which ensured that the row read/write cycle was completed at a given time. This allowed a new read command to be issued before the reading of the previous data word was completed, with confidence that the read would complete correctly and the reading of the new word would begin with minimal delay.

However, there were problems with alternating reading and writing. When several words of data were read in a row, there were no problems, but if before the end of the recording a command came to read the word that was being written, this could lead to reading incorrect data. Therefore, the synchronous memory controller has become even more complex, providing protection against such situations.

Also in SDRAM memory the number of memory matrices was increased from one to two, sometimes up to four. This made it possible, while accessing one memory matrix, to regenerate the rows of another matrix, which, in turn, made it possible to increase the clock frequency of the memory due to a decrease in regeneration delays.

This also made it possible to read data from several memory matrices at once. That is, while reading from one memory matrix is ​​in progress, the address of the new word for reading/writing is already being transferred to another.

Over time, the development of production technology and the ability to work with several memory matrices at once made it possible to significantly increase the internal speed of dynamic memory chips. The external memory bus became a bottleneck and slowed down work. As a result, a new type of memory, DDR SDRAM, was developed. With the advent of DDR SDRAM, the previous SDRAM memory began to be called SDR SDRAM (Single Data Rate DRAM).

2.5. DDR SDRAM.

DDR SDRAM (Double Data Rate SDRAM) – synchronous dynamic memory with random access and double data transfer frequency.

In this type of RAM, data exchange on the external bus occurs not only along the edge of the clock pulse, but also along the fall. As a result, without increasing the clock frequency of the external bus, the volume of transmitted information doubles.

But increasing the speed of the external data bus is not enough; it is necessary that the memory itself maintains such a speed. Since increasing the operating frequency of RAM is quite difficult, time-consuming and expensive, manufacturers resorted to a trick. Instead of increasing the memory clock speed, they increased the width of the internal data bus (from memory matrix cells to I/O buffers) and made it twice as large as the width of the external memory bus (from the memory controller built into the northbridge, or the processor to the chip memory). That is, in 1 clock cycle, as much data was read as could be transmitted via the external bus in only two clock cycles. At the same time, the width of the external data bus was 64 bits, and the internal one was 128 bits.

As a result, the first part of the data was transmitted from the memory chip along the edge of the clock pulse, and the second part along the fall. A similar situation occurred when writing data to memory. First, the first part of the data was received, and then the second, after which they were processed simultaneously.

However, due to overhead and the need to use a multiplexer to combine two parts of data transferred to RAM, and a demultiplexer to divide data read from memory into two parts, memory latency has increased significantly.

Latency is the time between requesting data from memory and the time when RAM starts producing the required data.

As a result, the actual performance of DDR memory, compared to SDR, has increased by only 30-40 percent.

The most popular DDR memory models operated at a clock frequency of 200 MHz, but were labeled DDR400. 400 meant the number of transactions (exchanges) per second. Indeed, with a clock frequency of 200 MHz and data transmission on the rise and fall of the clock pulse, 400 MTr will be performed per second. In this case, the internal frequency of the memory chip will also be 200 MHz.

With the advent of DDR memory, latency has become one of the relevant parameters for the operation of a memory chip. As a result, to roughly estimate memory performance, a concept called memory timings was introduced.

Timings are usually specified by a set of four numbers that determine the main memory delays in the clock cycles of the memory chip. Table 1 shows an example of decoding DDR266 memory timings (timings: 2.5-3-3-7) in the order of their location in the line.

Table 1. Decoding of RAM timings.

Using timings you can determine:

• the time required to read the first bit from memory when the desired line is already open - Tcl clock cycles;
• the time required to read the first bit from memory when the line is inactive – Trcd+ Tcl clock cycles;
• the time required to read the first bit from memory when another line is active is Trp+Trcd+Tcl clock cycles;

Timings can be changed (overclock the memory), along with the clock frequency, but the stability of the memory is not guaranteed, so you need to be extremely careful and careful when trying to make memory work with non-standard settings.

Table 2 shows the main certified DDR SDRAM standards and their parameters.

Table 2. Parameters of DDR SDRAM memory standards.

Raising the clock frequency of the memory chip above 200 MHz at that stage was extremely difficult. Naturally, there was memory operating at a clock frequency of 233, 250 and even 267 MHz, but these were uncertified standards and they were expensive.

As a result, memory developers continued to develop the DDR SDRAM memory architecture. The logical result of this development was DDR2 SDRAM memory.

2.6. DDR2 SDRAM.

In DDR2 SDRAM, the internal data bus width was doubled and became four times larger than the external data bus. As a result, at the same clock frequency of the external memory bus, the internal clock frequency of DDR2 SDRAM memory was half that of DDR SDRAM memory.

For comparison, let's take the top-end DDR memory (DDR400) and the first specification of DDR2 memory (DDR2-400). It would seem that since this is a new type of memory, it should work faster, but this was not the case at all. In practice, DDR2-400 memory was almost slower than DDR400 memory.

Let's find out why. And so, the first is the clock frequency of the external data bus. It was the same for both types of memory - 200 MHz, and the width of the external data bus was also the same - 64 bits. As a result, the performance of DDR2-400 memory could not be noticeably higher than that of DDR400 memory.

In addition, in DDR400 memory the width of the internal bus was only 2 times larger than the external one, while in DDR2-400 it was four times. As a result, the design of the multiplexer and demultiplexer of DDR2-400 memory is more complex. In addition, the data being read/written is not always located in one row of the memory matrix, as a result, it is impossible to read/write all data words at the same time; this feature has a more negative effect, the larger the width of the internal data bus, and it is naturally larger for the memory DDR2.

So what is the advantage of DDR2-400 memory? And the advantage is the clock speed of the memory chip. It was two times lower than the clock speed of the DDR-400 chip. This offered enormous potential for increasing memory performance and reducing power consumption.

As a result, memory with an external bus operating at a clock frequency of 400 MHz very quickly appeared. And later, in top-end DDR2 memory models, the external bus clock frequency reached 533 MHz, with a memory chip clock frequency of 266 MHz, and a peak theoretical bandwidth of 9.6 GB/s, which, despite the increased latency, significantly exceeded the capabilities of DDR memory.

Table 3 shows the main DDR2 SDRAM standards and their parameters.

* Standard timings may vary among different manufacturers and greatly depend on the quality of the element base.

Table 3. Parameters of DDR2 SDRAM memory standards.

At this point, the limit of the possibility of improving DDR2 memory in terms of frequency and latency was practically reached. Further increases in performance led to a significant increase in power consumption and heat dissipation, and a decrease in the stability and reliability of memory.

As a result, in 2005, developers presented prototypes of a new generation of DDR SDRAM memory - DDR3 SDRAM. However, mass production of this memory and market expansion began only in 2009.

2.7. DDR3 SDRAM.

The main direction of development of DDR3 SDRAM memory remains the same as that of DDR2 SDRAM. That is, the width of the internal memory data bus was again doubled, which led to a reduction in the internal memory clock speed by half. In addition, a new technological process was used in the production of memory, at the beginning – up to 90 nm, then – up to 65 nm, 50 nm, 40 nm, and apparently this is not the limit.

All this opened up further opportunities for developers to increase the clock frequency of the external memory bus, the clock purity of the memory chip itself, reduce the operating voltage and increase the memory capacity.

However, along with the increase in the width of the internal data bus, the latency of the memory has increased, and the design of the multiplexer/demultiplexer has become more complicated. In general, all the problems with DDR and DDR2 memory moved to DDR3 memory.

But, thanks to improvements in the technological process and memory architecture, it was possible to reduce the read/write cycle time, which made it possible to somewhat reduce the impact of increased latency on memory performance.

Table 3 shows the existing DDR3 SDRAM standards and their main parameters.

* Standard timings may vary among different manufacturers and greatly depend on the production process and the quality of the element base.

Table 4. Parameters of DDR3 SDRAM standards.

DDR3 memory today (beginning of 2012) occupies a dominant position in the market, but it is already being replaced by a new generation of DDR memory - DDR4 SDRAM.

2.8. DDR4 SDRAM.

The new generation of memory standards were presented back in 2008 in San Francisco at a forum organized by Intel. In 2011, Samsung demonstrated its first prototypes of DDR4 memory. However, the start of production of this type of memory is planned for 2012, and the final conquest of the market will end no earlier than 2015. Such late dates for the start of mass production are mainly due to the fact that the capabilities of DDR3 memory have not yet been completely exhausted and can satisfy the requirements of most users. And, therefore, entering the market with a new type of memory will be commercially unjustified.

DDR4 memory will continue the trend of DDR memory. The width of the internal bus will be increased, the production technology will be improved to 32-36 nm, the clock frequencies of the external and internal bus will be raised, and the voltage will also be reduced.

But we’ll talk about it in more detail when the first mass-produced memory samples appear, and now let’s summarize the review of dynamic memory and formulate its main advantages and disadvantages.

3. Advantages and disadvantages of dynamic memory.

Advantages of dynamic memory:

• low cost;
• high degree of packaging, allowing the creation of large-volume memory chips.

Disadvantages of dynamic memory:

• relatively low performance, since the process of charging and discharging a capacitor, even a microscopic one, takes much longer than switching the trigger;
• high latency, mainly due to the internal data bus, several times wider than the external one, and the need to use a multiplexer/demultiplexer;
• the need to regenerate the capacitor charge, due to its rapid self-discharge, due to its microscopic size.

There is much more dynamic memory in a computer than static memory, since DRAM is used as the main memory of the VM. Like SRAM, dynamic memory consists of a core (an array of electronic devices) and interface logic (buffer registers, data reading amplifiers, regeneration circuits, etc.). Although the number of types of DRAM has already exceeded two dozen, their cores are organized almost identically. The main differences are related to the interface logic, and these differences are also due to the scope of application of the microcircuits - in addition to the main memory of the VM, dynamic memory ICs are included, for example, in video adapters. The classification of dynamic memory chips is shown in Fig. 5.10.

To evaluate the differences between types of DRAM, let's first look at the algorithm for working with dynamic memory. For this we will use Fig. 5.6.

Unlike SRAM, the address of a DRAM cell is transferred to the microcircuit in two steps, first the column address and then the row address, which makes it possible to reduce the number of address bus pins by approximately half, reduce the size of the case and place a larger number of chips on the motherboard. This, of course, leads to a decrease in performance, since it takes twice as long to transfer the address. To indicate which part of the address is transmitted at a certain moment, two auxiliary signals RAS and CAS are used. When accessing a memory cell, the address bus is set to the address of the row. After the processes on the bus have stabilized, the RAS signal is applied and the address is written to the internal register of the microcircuit

Rice. 5.10. Classification of dynamic RAM: a - chips for main memory; b - chips for video adapters

memory. The address bus is then set to the column address and the CAS signal is issued. Depending on the state of the WE line, data is read from or written to the cell (the data must be placed on the data bus before writing). The interval between setting the address and issuing the RAS (or CAS) signal is determined by the technical characteristics of the microcircuit, but usually the address is set in one cycle of the system bus, and the control signal in the next. Thus, to read or write one cell of dynamic RAM, five clock cycles are required, in which the following occurs: issuing a row address, issuing a RAS signal, issuing a column address, issuing a CAS signal, performing a read/write operation (in static memory, the procedure takes only two up to three measures).

You should also remember the need to regenerate data. But along with the natural discharge of the capacitor, the electronic device also leads to a loss of charge over time when reading data from DRAM, so after each reading operation the data must be restored. This is achieved by writing the same data again immediately after reading it. When reading information from one cell, the data of the entire selected row is actually output at once, but only those that are in the column of interest are used, and all the rest are ignored. Thus, a read operation from one cell results in the destruction of the entire row's data and must be recovered. Data regeneration after reading is performed automatically by the interface logic of the chip, and this happens immediately after reading the line.

Now let's look at the different types of dynamic memory chips, starting with system DRAM, that is, chips designed to be used as main memory. At the initial stage, these were asynchronous memory chips, the operation of which is not strictly tied to the clock pulses of the system bus.

Asynchronous dynamic RAM. Asynchronous dynamic RAM chips are controlled by RAS and CAS signals, and their operation, in principle, is not directly related to bus clock pulses. Asynchronous memory is characterized by additional time spent on the interaction of memory chips and the controller. Thus, in an asynchronous circuit, the RAS signal will be generated only after a clock pulse arrives at the controller and will be perceived by the memory chip after some time. After this, the memory will produce data, but the controller will be able to read it only upon the arrival of the next clock pulse, since it must work synchronously with the rest of the VM devices. Thus, there are slight delays during the read/write cycle due to the memory controller and memory controller waiting.

MicrocircuitsDRAM. The first dynamic memory chips used the simplest method of data exchange, often called conventional. It allowed reading and writing a memory line only every fifth clock cycle (Fig. 5.11, A). The steps of such a procedure have been described previously. Traditional DRAM corresponds to the formula 5-5-5-5. Microcircuits of this type could operate at frequencies up to 40 MHz and, due to their slowness (access time was about 120 seconds), did not last long.

MicrocircuitsFPM DRAM. Dynamic RAM chips that implement FPM mode are also early types of DRAM. The essence of the regime was shown earlier. The reading circuit for FPM DRAM (Fig. 5.11, b) is described by the formula 5-3-3-3 (14 clock cycles in total). The use of a fast page access scheme reduced access time to 60 seconds, which, taking into account the ability to operate at higher bus frequencies, led to an increase in memory performance compared to traditional DRAM by approximately 70%. This type of chip was used in personal computers until about 1994.

MicrocircuitsEDO DRAM. The next stage in the development of dynamic RAM was ICs with hyperpage mode, access(HRM, Hyper Page Mode), better known as EDO (Extended Data Output - extended data retention time at the output). The main feature of the technology is the increased time of data availability at the output of the microcircuit compared to FPM DRAM. In FPM DRAM chips, the output data remains valid only when the CAS signal is active, which is why the second and subsequent row accesses require three clock cycles: a CAS switch to the active state, a data read clock, and a CAS switch to the inactive state. In EDO DRAM, on the active (falling) edge of the C AS signal, the data is stored in an internal register, where it is stored for some time after the next active edge of the signal arrives. This allows the stored data to be used when the CAS is already in an inactive state (Fig. 5.11, V)

In other words, timing parameters are improved by eliminating cycles of waiting for the moment of data stabilization at the output of the microcircuit.

The reading pattern of EDO DRAM is already 5-2-2-2, which is 20% faster than FPM. Access time is about 30-40 ns. It should be noted that the maximum system bus frequency for EDO DRAM chips should not exceed 66 MHz.

MicrocircuitsBEDO DRAM. EDO technology has been improved by VIA Technologies. The new modification of EDO is known as BEDO (Burst EDO). The novelty of the method is that during the first access, the entire line of the microcircuit is read, which includes consecutive words of the package. The sequential transfer of words (switching columns) is automatically monitored by the internal counter of the chip. This eliminates the need to issue addresses for all cells in a packet, but requires support from external logic. The method allows you to reduce the time of reading the second and subsequent words by another clock cycle (Fig. 5.11, d), due to which the formula takes the form 5-1-1-1.

5.11. Timing diagrams of various types of asynchronous dynamic memory with a packet length of four words: a - traditional DRAM; b - FPM FRAM; V- EDO DRAM;

G - BEDO DRAM

MicrocircuitsEDRAM. A faster version of DRAM was developed by Ramtron's subsidiary, Enhanced Memory Systems. The technology is implemented in FPM, EDO and BEDO variants. The chip has a faster core and internal cache memory. The presence of the latter is the main feature of the technology. The cache memory is static memory (SRAM) with a capacity of 2048 bits. The EDRAM core has 2048 columns, each of which is connected to an internal cache. When accessing any cell, the entire row (2048 bits) is read simultaneously. The read line is entered into SRAM, and the transfer of information to cache memory has virtually no effect on performance since it occurs in one clock cycle. When further accesses to cells belonging to the same row are made, the data is taken from the faster cache memory. The next access to the kernel occurs when accessing a cell that is not located in a line stored in the cache memory of the chip.

The technology is most effective when reading sequentially, that is, when the average access time for a chip approaches the values ​​characteristic of static memory (about 10 ns). The main difficulty is incompatibility with controllers used when working with other types of DRAM

Synchronous dynamic RAM. In synchronous DRAM, information exchange is synchronized by external clock signals and occurs at strictly defined points in time, which allows you to take everything from the bandwidth of the processor-memory bus and avoid wait cycles. Address and control information is recorded in the memory IC. After which the response of the microcircuit will occur through a clearly defined number of clock pulses, and the processor can use this time for other actions not related to accessing memory. In the case of synchronous dynamic memory, instead of the duration of the access cycle, they talk about the minimum permissible period of the clock frequency, and we are already talking about a time of the order of 8-10 ns.

MicrocircuitsSDRAM. The abbreviation SDRAM (Synchronous DRAM) is used to refer to “regular” synchronous dynamic RAM chips. The fundamental differences between SDRAM and the asynchronous dynamic RAM discussed above can be reduced to four points:

Synchronous method of data transfer to the bus;

Conveyor mechanism for packet forwarding;

Use of several (two or four) internal memory banks;

Transferring part of the functions of the memory controller to the logic of the microcircuit itself.

Memory synchronicity allows the memory controller to “know” when data is ready, thereby reducing the costs of waiting and searching cycles for data. Since data appears at the output of the IC simultaneously with clock pulses, the interaction of memory with other VM devices is simplified.

Unlike BEDO, the pipeline allows packet data to be transferred clock by clock, thanks to which the RAM can operate uninterruptedly at higher frequencies than asynchronous RAM. The advantages of a pipeline are especially important when transmitting long packets, but not exceeding the length of the chip line.

A significant effect is achieved by dividing the entire set of cells into independent internal arrays (banks). This allows you to combine access to a cell in one bank with preparation for the next operation in the remaining banks (recharging control circuits and restoring information). The ability to keep multiple lines of memory open simultaneously (from different banks) also helps improve memory performance. When accessing banks alternately, the frequency of accessing each of them individually decreases in proportion to the number of banks and SDRAM can operate at higher frequencies. Thanks to the built-in address counter, SDRAM, like BEDO DRAM, allows reading and writing in batch mode, and in SDRAM the packet length varies and in batch mode it is possible to read an entire memory line. The IC can be characterized by the formula 5-1-1-1. Despite the fact that the formula for this type of dynamic memory is the same as that of BEDO, the ability to operate at higher frequencies means that SDRAM with two 6 banks at a bus clock speed of 100 MHz can almost double the performance of BEDO memory.

MicrocircuitsDDR SDRAM. An important step in the further development of SDRAM technology was DDR SDRAM (Double Data Rate SDRAM - SDRAM with double the data transfer rate). Unlike SDRAM, the new modification produces data in burst mode on both edges of the synchronization pulse, due to which the throughput doubles. There are several DDR SDRAM specifications, depending on the system bus clock speed: DDR266, DDR333, DDR400, DDR533. Thus, the peak bandwidth of a DDR333 memory chip is 2.7 GB/s, and for DDR400 it is 3.2 GB/s. DDR SDRAM is currently the most common type of dynamic memory in personal VMs.

MicrocircuitsRDRAM, DRDRAM. The most obvious ways to increase the efficiency of a processor with memory are to increase the bus clock frequency or the sampling width (the number of simultaneously transferred bits). Unfortunately, attempts to combine both options encounter significant technical difficulties (as the frequency increases, the problems of electromagnetic compatibility worsen, and it becomes more difficult to ensure that all parallelly sent bits of information arrive at the same time to the consumer). Most synchronous DRAMs (SDRAM, DDR) use wide sampling (64 bits) at a limited bus frequency.

A fundamentally different approach to building DRAM was proposed by Rambus in 1997. It focuses on increasing the clock speed to 400 MHz while reducing the sample width to 16 bits. The new memory is known as RDRAM (Rambus Direct RAM). There are several varieties of this technology: Base, Concurrent and Direct. In all, clocking is carried out on both edges of clock signals (as in DDR), due to which the resulting frequency is 500-600, 600-700 and 800 MHz, respectively. The first two options are almost identical, but the changes in Direct Rambus technology are quite significant.

First, let's look at the fundamental points of RDRAM technology, focusing mainly on the more modern version - DRDRAM. The main difference from other types of DRAM is the original data exchange system between the core and the memory controller, which is based on the so-called “Rambus channel” using an asynchronous block-oriented protocol. At the logical level, information between the controller and memory is transferred in packets.

There are three types of packages: data packages, row packages and column packages. Packets of rows and columns are used to transmit commands from the memory controller to control the rows and columns of the array of storage elements, respectively. These commands replace the conventional chip control system using RAS, CAS, WE and CS signals.

The GE array is divided into banks. Their number in a crystal with a capacity of 64 Mbit is 8 independent or 16 dual banks. In dual banks, the pair of banks share common read/write amplifiers. The internal core of the chip has a 128-bit data bus, which allows 16 bytes to be transferred at each column address. When recording, you can use a mask in which each bit corresponds to one byte of the packet. Using the mask, you can specify how many bytes of the packet and which bytes should be written to memory.

The data, row and column lines in the channel are completely independent, so row commands, column commands and data can be transmitted simultaneously, and for different banks of the chip. Column packets contain two fields and are transmitted over five lines. The first field specifies the main write or read operation. The second field contains either an indication of the use of a record mask (the mask itself is transmitted over the data lines), or an extended operation code that defines an option for the main operation. String packets are divided into activation, cancellation, regeneration and power mode switching commands. Three lines are allocated for transmitting string packets.

The write operation can immediately follow the read - only a delay is needed for the time the signal travels through the channel (from 2.5 to 30, not depending on the length of the channel). To equalize delays in the transmission of individual bits of the transmitted code, the conductors on the board must be positioned strictly in parallel, have the same length (the length of the lines should not exceed 12 cm) and meet strict requirements defined by the developer.

Each write in the channel can be pipelined, with the first data packet having a latency of 50 ns, and the remaining read/write operations occurring continuously (latency is only introduced when changing an operation from write to read, and vice versa).

Available publications mention the work of Intel and Rambus on a new version of RDRAM, called nDRAM, which will support data transfer at frequencies up to 1600 MHz.

MicrocircuitsSLDRAM. A potential competitor to RDRAM as a memory architecture standard for future personal VMs is a new type of dynamic RAM developed by the SyncLm Consortium, a consortium of VM manufacturers, known by the abbreviation SLDRAM. Unlike RDRAM, the technology of which is the property of Rambus and Intel, this standard is open. At the system level, the technologies are very similar. Data and commands from the controller to memory and back to SLDRAM are transmitted in packets of n or 8 parcels. Commands, address and control signals are sent over a unidirectional 10-bit command bus. Read and write data is supplied over a bidirectional 18-bit data bus. Both buses operate at the same frequency. For now, this frequency is still 200 MHz, which, thanks to DDR technology, is equivalent to 400 MHz. The next generations of SLDRAM should operate at frequencies of 400 MHz and higher, that is, provide an effective frequency of more than 800 MHz.

Up to 8 memory chips can be connected to one controller. To avoid delays in signals from chips further away from the controller, the timing characteristics for each chip are determined and entered into its control register when the power is turned on.

MicrocircuitsESDRAM. This is a synchronous version of EDRAM that uses the same techniques to reduce access time. A write operation, unlike a write operation, bypasses the cache, which increases FSDRAM performance when resuming reading from a line already in the cache. Thanks to the presence of two banks in the chip, downtime due to preparation for read/write operations is minimized. The disadvantages of the microcircuit under consideration are the same as those of EDRAM - the controller is more complex, since it must take into account the possibility of preparing to read a new kernel line into the cache memory. In addition, with an arbitrary sequence of addresses, the cache memory is used inefficiently.

MicrocircuitsCDRAM. This type of RAM was developed by Mitsubishi Corporation, and it can be considered as a revised version of ESDRAM, free from some of its imperfections. The capacity of the cache memory and the principle of placing data in it have been changed. The capacity of a single cache block has been reduced to 128 bits, so the 16-kilobit cache can simultaneously store copies of 128 memory locations, allowing for more efficient use of the cache. Replacement of the first memory section placed in the cache begins only after the last (128th) block is filled. The means of access have also changed. Thus, the chip uses separate address buses for the static cache and the dynamic core. Transferring data from the dynamic core to cache memory is combined with issuing data to the bus, so frequent but short transfers do not reduce the performance of the IC when reading large amounts of information from memory and put CDRAM on par with ESDRAM, and when reading at selective addresses, CDRAM clearly wins. It should be noted, however, that the above changes led to even greater complexity of the memory controller.

Random access memory (RAM) is an integral part of microprocessor systems for various purposes. RAM is divided into two classes: static and dynamic. In static RAM, information is stored using flip-flops, while in dynamic RAM, information is stored using capacitors with a capacity of about 0.5 pF. The duration of information storage in static RAM is not limited, while in dynamic RAM it is limited by the self-discharge time of the capacitor, which requires special means of regeneration and additional time spent on this process.

Structurally, any RAM consists of two blocks - a matrix of storage elements and an address decoder. For technological reasons, the matrix most often has a two-coordinate decoding of the address - in rows and columns. In Fig. Figure 9.45 shows the matrix of a 16-bit SRAM. The matrix consists of 16 memory cells mem_i, the diagram of which is shown in Fig. 9.46. Each memory cell is addressed by inputs X, Y by selecting address lines by decoder along the lines AxO...Ax3 and columns AyO...Ay3 (see Fig. 9.45) and supplying a logical one signal along the selected lines. In this case, a two-input AND element (U1) is triggered in the selected memory cell, preparing circuits for reading and writing information on the input DIO...DI3 or output DOO...D03 bit buses. The enabling signal for issuing an address is CS (chip select), which is fed to the enable input of the address counter (Addr_cnt) or the same input of decoders connected to the counter outputs.

When writing to a memory cell (see Fig. 9.46), 1 or 0 is set on the corresponding bit bus, signal 1 is set at the WR/RD input, and after gating the counter or address decoders with the CS signal, elements 2I U1, U2 are triggered. Positive edge of the signal with element U2 is supplied to the clock input of the D-flip-flop U4, as a result of which 1 or 0 is written in it, depending on the signal level at its D-input.

When reading from a memory cell, the WR/RD" input is set to 0, and elements U1, U3, U5 are triggered and an enabling signal is sent to the OUTPUT ENABLE input of the buffer element U6, as a result of which the signal from the Q-output of the D-flip-flop is transmitted to the bit bus DOO...D03. To check the functioning of the memory cell, a word generator is used (Fig. 9.47).

Modern static storage devices are characterized by high performance and are used to a limited extent in microprocessor systems due to their relatively high cost. In such systems they are used only as so-called cache memory. Cache (reserve) refers to a high-speed buffer memory between the processor and main memory, which serves to partially compensate for the difference in the speed of the processor and main memory - the most frequently used data is stored in it. When the processor accesses a memory cell for the first time, its contents are copied in parallel to the cache, and if accessed again, it can be retrieved from it at a much higher speed. When writing to memory, information enters the cache and is simultaneously copied into memory (Write Through scheme) or copied after some time (Write Back scheme). With write-back, also called buffered write-through, information is copied into memory in the first free clock cycle, and with delayed write (Delayed Write) - when there is no free space to place a new value in the cache; in this case, relatively rarely used data is forced out into the main RAM. The second scheme is more efficient, but also more complex due to the need to maintain consistency between the contents of the cache and main memory.

Cache memory consists of a data area divided into blocks (lines), which are elementary units of information when the cache operates, and a tag area that describes the state of the lines (free, busy, marked for additional recording, etc.). Basically, two cache organization schemes are used: direct mapped, when each memory address can be cached by only one line (in this case, the line number is determined by the low-order bits of the address), and ra-way associative, when each address can be cached in several lines. An associative cache is more complex, but allows for more flexible caching of data; The most common are four-link caching systems.

Microprocessors 486 and higher also have an internal cache of 8...16 KB. It is also designated as Primary (primary) or LI (Level I - first level) in contrast to the external one (External), located on the board and designated Secondary (secondary) or L2. In most processors, the internal cache operates according to a direct write scheme, but in the 486 (Intel P24D processor and the latest DX4-100, AMD DX4-120, 5x86) and Pentium it can also work with lazy write. The latter requires special support on the part of the motherboard so that when exchanging via DMA (direct memory access to input/output devices), data consistency in memory and the internal cache can be maintained. Pentium Pro processors also have a built-in L2 cache of 256 or 512 KB.

In microprocessor systems, dynamic RAM with a storage capacitor, which is very versatile, is most often used as RAM. We provide data on the most common types of such RAM.

In dynamic memory, cells are made on the basis of areas with accumulation of charges, occupying a much smaller area than flip-flops, and consuming practically no energy when storing information. When a bit is written to such a cell, an electrical charge is formed in it, which remains for several milliseconds; To permanently maintain the cell's charge, it is necessary to regenerate (rewrite) its contents. The cells of dynamic memory chips are also organized in the form of a rectangular matrix; When accessing a microcircuit, the matrix row address is first supplied to its inputs, accompanied by a RAS signal (Row Address Strobe), then, after some time, a column address is supplied, accompanied by a CAS signal (Column Address Strobe). Each time a single cell is accessed, all cells of the selected row are regenerated, so to completely regenerate the matrix, it is enough to iterate through the row addresses. Dynamic memory cells have a relatively low speed (tens - hundreds of nanoseconds), but a high specific density (of the order of several megabytes per case) and lower power consumption.

Conventional RAM is often called asynchronous, since setting the address and supplying control signals can be performed at arbitrary times; it is only necessary to observe the timing relationships between these signals. They include the so-called guard intervals necessary for establishing signals. There are also synchronous types of memory that receive an external clock signal, the pulses of which are strictly linked to the moments of address submission and data exchange; they allow greater use of internal pipelining and block access.

FPM DRAM (Fast Page Mode DRAM - dynamic memory with fast page access), has been actively used recently. Page-access memory differs from conventional dynamic memory in that, after selecting a matrix row and holding the RAS signal, it allows multiple settings of the column address gated by the CAS signal, as well as rapid regeneration according to the “CAS before RAS” scheme. The first allows you to speed up block transfers, when the entire data block or part of it is located inside one row of the matrix, called a page in this system, and the second allows you to reduce the time spent on memory regeneration.

EDO (Extended Data Out) are actually ordinary FPM chips with data latching registers installed at the output. During page exchange, such microcircuits operate in simple pipeline mode: they hold the contents of the last selected cell at the data outputs, while the address of the next selected cell is already supplied to their inputs. This makes it possible to speed up the process of reading sequential data arrays by approximately 15% compared to FPM. With random addressing, such memory is no different from ordinary memory.

BEDO (Burst EDO - EDO with block access) - EDO-based memory that operates not in single, but in batch read/write cycles. Modern processors, thanks to internal and external caching of instructions and data, exchange predominantly blocks of words of maximum width with main memory. With BEDO memory, there is no need to constantly supply successive addresses to the inputs of microcircuits while observing the required time delays; it is enough to gate the transition to the next word with a separate signal.

SDRAM (Synchronous DRAM - synchronous dynamic memory) - synchronous access memory that works faster than conventional asynchronous (FPM/EDO/BEDO). In addition to synchronous access, SDRAM uses an internal division of the memory array into two independent banks, which allows you to combine access from one bank with setting an address in another. SDRAM also supports block swapping. The main advantage of SDRAM is its support for sequential access in synchronous mode, where no additional wait clocks are required. With random access, SDRAM operates at almost the same speed as FPM/EDO.

PB SRAM (Pipelined Burst SRAM - static memory with block pipeline access) is a type of synchronous SRAM with internal pipelining, which approximately doubles the speed of data block exchange.

In addition to the main RAM, a memory device is also supplied with an information display device - a video display system. This memory is called video memory and is located on the video adapter board.

Video memory is used to store images. The maximum possible resolution of the video card depends on its volume - AxBxC, where A is the number of horizontal pixels, B - vertically, C - the number of possible colors of each pixel. For example, for a resolution of 640x480x16 it is enough to have a video memory of 256 KB, for 800x600x256 - 512 KB, for 1024x768x65536 (another designation is 1024x768x64k) - 2 MB, etc. Since colors are stored in an integer number of bits, the number of colors is always an integer power of 2 (16 colors - 4 bits, 256 - 8 bits, 64k - 16, etc.).

Video adapters use the following types of video memory.

FPM DRAM (Fast Page Mode Dynamic RAM - dynamic RAM with fast page access) is the main type of video memory, identical to that used in motherboards. Actively used until 1996. The most common FPM DRAM chips are four-bit DIP and SOJ, as well as sixteen-bit SOJ.

VRAM (Video RAM) is a so-called dual-port DRAM that supports simultaneous access by the video processor and the computer's central processor. Allows you to combine in time the display of an image on the screen and its processing in video memory, which reduces delays and increases operating speed.

EDO DRAM (Extended Data Out DRAM - dynamic RAM with extended output data retention time) - memory with pipelining elements that allows you to somewhat speed up the exchange of data blocks with video memory.

SGRAM (Synchronous Graphics RAM) is a variant of DRAM with synchronous access, when all control signals change simultaneously with the system clock signal, which reduces time delays.

WRAM (Window RAM - window RAM) - EDO VRAM, in which the window through which the video controller accesses is made smaller than the window for the central processor.

MDRAM (Multibank DRAM - multi-bank RAM) is a variant of DRAM, organized in the form of many independent banks of 32 KB each, operating in a pipeline mode.

Increasing the speed at which the video processor accesses video memory, in addition to increasing the adapter's bandwidth, allows you to increase the maximum frequency of image regeneration, which reduces eye fatigue for the operator.

Memory chips have four main characteristics - type, size, structure and access time. Type indicates static or dynamic memory, capacity indicates the total memory capacity, and structure indicates the number of memory cells and the width of each cell. For example, 28/32-pin DIP SRAM chips have an 8-bit structure (8kx8, 16kx8, 32kx8, 64kx8, 128kx8), the 256 KB cache consists of eight 32kx8 chips or four 64kx8 chips (we are talking about the data area, additional chips may have a different structure for storing features). It is no longer possible to install two 128kx8 microcircuits, since you need a 32-bit data bus, which only four microcircuits can provide. Common RF SRAMs in 100-pin PQFP packages have a 32-bit 32kx32 or 64kx32 structure and are used in twos or fours on Pentium boards.

30-pin SIMMs have an 8-bit structure and are used with two processors 286, 386SX and 486SLC, and four with 386DX, 486DLC and regular 486DX. 72-pin SIMMs have a 32-bit structure and can be used with the 486DX one at a time, and two with the Pentium and Pentium Pro. 168-pin DIMMs have a 64-bit structure and are used in the Pentium and Pentium Pro one at a time. Installing memory modules or cache chips in quantities greater than the minimum for a given system (motherboard) allows you to speed up work with them using the interleave principle.

Access time characterizes the speed of the microcircuit and is usually indicated in nanoseconds after the dash at the end of the name. On slower microcircuits, only the first digits can be indicated (-7 instead of -70, -15 instead of -150); on faster static ones, “-15” or “-20” indicates the real access time to the cell. Often, microcircuits indicate the minimum of all possible access times, for example, it is common to mark 50 EDO DRAM instead of 70, or 45 instead of 60, although such a cycle is only achievable in block mode, and in single mode the microcircuit still has an access time of 70 or 60 ns. A similar situation occurs in the marking of PB SRAM: 6 instead of 12, and 7 instead of 15. SDRAM chips are usually marked with access time in block mode (10 or 12 ns).

Memory ICs are implemented in the following types of packages.

DIP (Dual In line Package - a package with two rows of pins) - classic chips used in the main memory units of the IBM PC/XT and early PC/AT are now used in cache memory units.

SIP (Single In line Package - package with one row of pins) - a microcircuit with one row of pins, installed vertically.

SIPP (Single In line Pinned Package - a module with one row of needle pins) - a memory module inserted into the panel like DIP/SIP chips; used in early IBM PC/AT.

SIMM (Single In line Memory Module - memory module with one row of contacts) - a memory module inserted into a clamp connector; used in all modern boards, as well as in many adapters, printers and other devices. SIMM has contacts on both sides of the module, but they are all connected to each other, forming, as it were, one row of contacts. Currently, SIMMs are mainly equipped with FPM/EDO/BEDO chips.

DIMM (Dual In line Memory Module - a memory module with two rows of contacts) is a memory module similar to a SIMM, but with separate contacts (usually 2x84), thereby increasing the capacity or number of memory banks in the module. Mainly used in Apple computers and new P5 and P6 boards. EDO/BEDO/SDRAM chips are installed on DIMMs.

CELP (Card Egde Low Profile - a low card with a blade connector on the edge) is an external cache memory module assembled on SRAM (asynchronous) or PB SRAM (synchronous) chips. It is similar in appearance to a 72-pin SIMM and has a capacity of 256 or 512 KB. Another name is COAST (Cache On A STick - literally “cache on a stick”).

Dynamic memory modules, in addition to the main memory cells, can have additional cells for storing parity bits (Parity) for data bytes; such SIMMs are sometimes called 9- and 36-bit modules (one parity bit per byte of data). Parity bits are used to control the correctness of reading data from the module, allowing you to detect some errors (see Section 9.7). It makes sense to use modules with parity bits only where very high reliability is needed. Carefully tested modules without parity bits are also suitable for normal applications, provided that the motherboard supports these types of modules.

The easiest way to determine the type of module is by marking and the number of memory chips on it: for example, if a 30-pin SIMM has two chips of one type and another of another, then the first two are main (each has four bits), and the third is intended for storage parity bits (it is single-bit).

In a 72-pin SIMM with twelve chips, eight of them store data and four of them store parity bits. Modules with 2, 4, or 8 chips do not have memory to store parity bits.

Sometimes modules are equipped with a so-called parity simulator - an adder chip that always produces the correct parity bit when reading a cell. This is mainly intended for installing such modules in boards where parity check is not disabled.

The 72-pin SIMMs have four dedicated PD (Presence Detect) lines on which up to 16 signal combinations can be configured using jumpers. PD lines are used in some motherboards to determine the presence of memory modules in the slots and their parameters (volume and speed). Most universal boards produced by third parties, as well as the SIMMs they produce, do not use PD lines.

DIMMs in accordance with the JEDEC specification implement PD technology using a serial EEPROM called Serial Presence Detect (SPD). The ROM is an 8-pin chip located in the corner of the DIMM board, and its contents describe the configuration and parameters of the module. Motherboards with 440LX/BX chipsets can use SPD to configure the memory management system. Some motherboards can do without SPD, defining the configuration of modules in the usual way.

Test questions and assignments

1. What types of memory are there?

2. Simulate the static memory cell in Fig. 9.46. The task of the simulation is to select binary combinations for the signals at the cell input and register the result at the cell output using the IND indicator.

3. Based on the diagram in Fig. 9.45 design a four-bit RAM circuit using a word generator. At the same time, in the diagram in Fig. 9.45 use only 4 low addresses (two in rows and two in columns) and, accordingly, only two data buses (two input and two output). Connect indicators to the output buses.

4. Where is static memory used in modern computers?

5. How does dynamic memory differ from static memory?

6. What types of dynamic memory are used in modern computers?

7. What is video memory and how is it related to the characteristics of the information displayed on the display?

8. What types of memory are used as video memory?

9. What design do memory chips have?

Types of RAM.

Random access memory is memory for temporary storage of commands and data used during computer operation. It provides quick access to the required information to the processor, video card and other computer elements, and temporary storage of the results of their work.

In principle, RAM can include any type of memory, both non-volatile and dependent, but with sufficient speed, scalability and reliability to support the operation of the processor and other fast computer components.

However, at the moment, RAM can be divided into three types:

1. Dynamic memory (DRAM) is a volatile semiconductor random access memory in which each digit is stored in a capacitor that requires constant regeneration to store information.

2. Static memory (SRAM) is a volatile semiconductor random access memory in which each bit is stored in a flip-flop that allows the bit to be maintained without constant rewriting.

3. Magnetoresistive random access memory (MRAM) is a non-volatile random access memory device that stores information using magnetic moments, namely the direction of magnetization of the ferromagnetic layer of the memory cell.

This division will be correct only if you do not take into account outdated types of memory, such as memory on mercury delay lines, storage cathode ray tubes (CRT), memory on magnetic cores, and so on, described in the article “First Generation Computers”.

And promising developments such as:

FRAM (Ferroelectric Random Access Memory) is a ferroelectric memory based on ferroelectrics - dielectrics capable of changing the dipole moment under the influence of temperature and an external electric field;

PCM (Phase Change Memory) – memory based on a change in the phase state of a substance (Halcogenide) from crystalline to amorphous and back;

PMC (Programmable Metallization Cell) – memory based on programmable metallization of a cell, based on changing the position of atoms under the influence of an electric charge;

RRAM (Resistive Random-Access Memory) is a resistive memory built on the basis of elements capable of changing their resistance depending on the amount of current passed through them;

and many other types of memory that have not yet entered the market on a large scale or are generally at the stage of development or laboratory testing.

Moreover, the operating principle of many of the types of memory considered promising today was developed ten or more years ago, but due to the high cost or complexity of production, these types of memory did not become popular, or their development was not completed at all. And only now they paid close attention.

Dynamic RAM.

Dynamic Random Access Memory (DRAM) is a volatile semiconductor memory with random access. At the moment, this is the main type of RAM used in modern personal computers and provides the best price-quality ratio compared to other types of RAM. However, demands for speed, power consumption and reliability of RAM are constantly increasing, and dynamic RAM is already struggling to meet modern needs, so we can expect competing types of RAM, such as magnetoresistive RAM, to become commercially available in the coming years.

1. Dynamic random access memory device.
1.1. Dynamic memory performance at rest.
1.2. Dynamic memory operation when reading data and regenerating.
1.3. Dynamic memory operation when writing data.
2. Stages of modernization of dynamic random access memory.
2.1. PM DRAM.
2.2. FPM DRAM.
2.3. EDO-DRAM.
2.4. SDRAM.
2.5. DDR SDRAM.
2.6. DDR2 SDRAM.
2.7. DDR3 SDRAM.
2.8. DDR4 SDRAM.
3. Advantages and disadvantages of dynamic memory.

Dynamic random access memory device.

Dynamic Random Access Memory (DRAM) is a volatile random access memory, each cell of which consists of one capacitor and several transistors. The capacitor stores one bit of data, and the transistors act as switches that hold the charge in the capacitor and allow access to the capacitor when reading and writing data.

However, the transistors and capacitor are not ideal, and in practice the charge from the capacitor runs out quite quickly. Therefore, periodically, several tens of times per second, it is necessary to recharge the capacitor. In addition, the process of reading data from dynamic memory is destructive, that is, when reading, the capacitor is discharged, and it is necessary to recharge it again so as not to permanently lose the data stored in the memory cell.

In practice, there are different ways to implement dynamic memory. A simplified block diagram of one of the implementation methods is shown in Figure 1.

As can be seen from the figure, the main memory block is a memory matrix, consisting of many cells, each of which stores 1 bit of information.

Each cell consists of one capacitor (C) and three transistors. Transistor VT1 allows or prohibits writing new data or cell regeneration. Transistor VT3 acts as a key that keeps the capacitor from discharging and allows or prohibits reading data from the memory cell. Transistor VT2 is used to read data from the capacitor. If there is a charge on the capacitor, then the transistor VT2 is open, and the current will flow along line AB, respectively, there will be no current at the output Q1, which means that the cell stores a bit of information with a zero value. If there is no charge on the capacitor, then capacitor VT2 is closed, and the current will flow through line AE, accordingly, there will be current at the output Q1, which means that the cell stores a bit of information with the value “one”.

The charge in the capacitor, used to maintain transistor VT2 in the open state while current passes through it, is quickly consumed, so when reading data from the cell, it is necessary to regenerate the capacitor charge.

For dynamic memory to work, voltage must always be supplied to the matrix; in the diagram it is indicated as Up. With the help of resistors R, the supply voltage Up is evenly distributed between all columns of the matrix.

The memory also includes a memory bus controller, which receives commands, addresses and data from external devices and relays them to internal memory blocks.

Commands are transmitted to the control unit, which organizes the operation of the remaining blocks and periodic regeneration of memory cells.

The address is converted into two components - a row address and a column address, and is transmitted to the appropriate decoders.

The line address decoder determines which line needs to be read or written from and outputs a voltage to that line.

The column address decoder, when reading data, determines which of the read data bits have been requested and should be issued to the memory bus. When writing data, the decoder determines which columns to send write commands to.

The data processing unit determines what data needs to be written to which memory cell, and produces the corresponding data bits to be written to these cells.

Regeneration blocks define:

• when data is being read and it is necessary to regenerate the cell from which the data was read;
• when data is being written, and, therefore, there is no need to regenerate the cell.

The data buffer stores the entire read row of the matrix, since when reading the entire row is always read, it then allows you to select the required data bits from the read row.

Let's consider the principle of operation of dynamic memory using the example of the block diagram shown in Figure 1. We will consider working with the first cell (M11). The operation of the remaining memory cells is completely identical.