Printed circuit board layout technique. PCB layout

1 General provisions

To prevent problems with electrostatics and noise, certain rules must be followed when laying out the printed circuit board. The most critical point is pin C, because it is connected to the built-in 3.3-volt power supply of the MK core. Therefore, the filter capacitor should be located as close to the terminal as possible.

You should also pay close attention to the wiring of the power and ground circuits. The food is supplied by a “star”. We recommend placing a layer of earth on the installation side directly under the MK body. The Vcc and Vss lines should have only one connection point with the rest of the circuit to avoid interference on the MK and from the MK. Filter capacitors (DeCaps) should be located as close as possible to the corresponding terminals. If they are removed too far, they cease to perform their function.

When using quartz resonators, they should be located at a minimum distance from the Xn(A) terminals.

If possible, it is advisable to place filter capacitors on the MK mounting side.

2 Power supply wiring

The Vcc and Vss buses need to be routed not in a series chain, but in a “star”. For Vss, an earthen polygon under the MK body is recommended, connected at one point to the rest of the circuit.

Below are two examples of bad and good power supply wiring.

3 Filtering output C

4 Filtering power circuits

Filter capacitors (DeCaps) for power circuits must be located in the path of power currents, otherwise their use does not make sense. The following figure explains this statement:

5 Location of the quartz resonator and wiring of signal circuits

Quartz should be located as close to the MK as possible. Thus, the generator capacitors will be located “behind” the quartz.

6 Additional documentation

Additional more detailed information contained in Application Note 16bit-EMC-Guideline.

7 List of MK conclusions

The table shows the MK pins that are critical to electromagnetic interactions and brief information about their connection.

* - may not be present in a specific MK

Little secrets of routing boards with operational and instrumentation amplifiers

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When designing boards
Nothing comes so cheap
And not valued so highly
How to properly trace.

In the age of the Internet of things and the availability of printed circuit boards, and not only using LUT technology, their design is often carried out by people whose entire activity is related to digital technology.

Even when routing a simple digital board, there are unspoken rules that I always follow in my projects, and in the case of development measuring devices with digital-to-analog sections of circuits this is simply necessary.

In this article, I want to direct novice designers to a number of elementary techniques that should be followed in order to obtain a stable operating circuit and reduce the measurement error or minimize the distortion coefficient of the audio path. For clarity, the information is presented in the form of two examples.

Example number two. Tracing a simple op-amp circuit

Rice. 2. Two options for tracing the amplifier board to the op-amp

A small off-topic, not directly related to the topic of today’s article

I strongly advise you to use the same technique when supplying power to other types of microcircuits, especially ADCs, DACs and numerous power pins of microcontrollers. If you use built-in analog microcontroller modules - ADC, DAC, comparators, reference voltage sources, do not be lazy to look at the datasheet and see which blocking capacitors, in what quantity, and where should be installed. An decoupling circuit in the form of a filter or at least a resistance between the main digital power supply of the microcontroller and the analog one would not hurt. It is better to place the analog ground as a separate polygon or screen layer, and connect it to the main ground at one point, in some cases it is useful through a filter

Let's move on to a more serious and interesting case from the field of measurements, where tracing can be extremely important.

Example number one. Tracing a current consumption monitor on an instrumentation amplifier

Rice. 3. Current monitor circuit using instrumentation op-amp

The figure shows a diagram of a current consumption meter. The measuring element is the shunt resistance included in the power circuit. The load at which the current is measured is R load. The measured voltage is removed from the resistance R shunt and filtered using a symmetrical circuit on elements R1, R2, C1-C3. Chip U2 serves to supply the reference voltage. R4, C5 - output filter.

When tracing, of course, you must follow all the recommendations given above.

Rice. 4. Two options for routing the amplifier board on an instrumentation op-amp

Let's look at the shortcomings that the left diagram has:

• Since we have a differential input, it is necessary to make its two signal paths as symmetrical as possible. The signal line conductors must be of the same length and located close to each other. Ideally at the same distance from each other;
• The reference follower IC must be located as close as possible to the reference voltage input of the instrumentation amplifier.

In this section, we look at how to avoid digital signal distortion associated with its transmission along a conductor on a printed circuit board. Although this is primarily a task for the circuit engineer, the PCB designer is also often to blame for problems with signal transmission on the board, as well as crosstalk and crosstalk occurring on the board.

Why is the signal distorted during transmission?
First of all, distortion is characteristic of high-frequency signals, with a frequency of 1 GHz or more. This is due to the effects of resonances and reflections on individual wire segments, vias, fan-outs on the board, and at the receiver inputs. However, the problem is that signals with a frequency of up to 500 MHz, typical for standard digital circuits, as we will see later, can often be significantly distorted, which means they can also be classified as high-frequency.

What is the idea of ​​transmission without distortion?
The principle of signal transmission without distortion is that the conductor is made as a transmission line (or “long line”) with a given characteristic (wave) impedance, i.e. impedance Z 0 , the same along the entire length from the source to the signal receiver, which ensures the homogeneity of the line. The second requirement is the consistency of the line with the source and receiver of the signal. Unlike a conventional conductor, such a transmission line does not lead to resonance, distortion and reflection during signal transmission, no matter how long it is. Transmission lines can be easily implemented on a printed circuit board by using materials with known parameters and ensuring the required dimensions of the printed pattern elements. There are serial and parallel line matching, and it is necessary to use certain matching resistors at the source output and/or signal receiver input. The transmission lines formed on the board can, of course, be extended outside the board using connectors and cables with controlled characteristic impedance Z 0 .

For which signals does distortion become significant?
By comparing the length of the conductor on the board with the wavelength of the highest frequency component of the transmitted signal (when propagating, for example, in FR4 material), the so-called electrical length of the conductor can be determined. The electrical length can be expressed in fractions of the minimum wavelength or in fractions of its inverse value - the front duration. If the conductor has too much electrical length, then to prevent excessive signal distortion, this conductor must be configured as a transmission line. Note that when transmitting high-frequency signals, transmission lines should be used not only to reduce distortion, but also to reduce the level of electromagnetic radiation (EMR).

Rule of "half the duration of the front"
A rough rule is that the conductor is "electrically long" (what is called in electrical engineering "long line"), if the time it takes for the signal front to pass from the source to the farthest receiver exceeds half the signal front time. It is in this case that reflections in the line can significantly distort the signal front. Let's assume that the device contains chips with a rise time of 2 ns (for example, according to the documentation for the FastTTL series). Dielectric constant of PCB material (FR4) on high frequencies is close to 4.0, which gives the speed of the front about 50% of the speed of light, or 1.5.10 8 m/s. This corresponds to a front propagation time of 6.7 ps/mm. With this speed, the front will travel about 300 mm in 2 ns. From this we can conclude that for such signals "transmission lines" should only be used if the conductor length exceeds half of this distance - that is, 150 mm.

Unfortunately, this is the wrong answer. The "half rise time" rule is too simplistic and can lead to problems if its shortcomings are not taken into account.

Problems with the simplified approach
The data on the rise time given in the documentation for the microcircuits reflect maximum value, and often real time switching is significantly less (say, it can be 3-4 times less than the “maximum” one, and it is hardly possible to guarantee that it will not change from batch to batch of chips). Moreover, the inevitable capacitive component of the load (from the line-connected IC inputs) reduces the signal propagation speed compared to the design speed achievable on a bare circuit board. Therefore, to achieve adequate transmitted signal integrity, transmission lines should be used with much shorter conductors than the previously described rule suggests. It can be shown that for signals with a rise time (according to the documentation) of 2 ns, it is advisable to use transmission lines for conductors whose length exceeds only 30 mm (and sometimes less)! This especially applies to signals that carry a synchronization or gating function. It is precisely these signals that are characterized by problems associated with “false positives,” “recalculation,” “recording of incorrect data,” and others.

How to design transmission lines?
There are many publications devoted to what types of transmission lines there can be, how to design them on a printed circuit board, and how to check their parameters. In particular, the IEC 1188-1-2: 1988 standard provides detailed guidance in this regard. There are also many software products available that allow you to select transmission line design and PCB structure. Majority modern systems PCB designs come with built-in programs that allow the designer to design transmission lines with specified parameters. Examples include programs such as AppCAD, CITS25, TXLine. Most full capabilities provided by software products from Polar Instruments.

Examples of transmission lines
As examples, consider the simplest types of transmission lines.

How to design the transmission line in the best way?
The highest speed (or most critical) signals should be in layers adjacent to the ground plane (GND), preferably one that is paired with the decoupling power plane. Less critical signals can be applied to power plans if the plans are adequately decoupled and are not very noisy. Each such power plan must be associated with the microcircuit from which or to which this signal is received. The best noise immunity and EMC are provided by strip lines drawn between two GND plans, each of which is paired with its own power plan for decoupling.
The transmission line must not have holes, breaks or splits in any of the reference plans to which it is drawn, as this will lead to significant changes in Z 0 . Moreover, the strip line should be as far as possible from any breaks in the plan or from the edge of the reference plan, and given distance should not be less than ten times the width of the conductor. Adjacent transmission lines must be separated by at least three conductor widths to eliminate crosstalk. Very critical or "aggressive" signals (such as communication with a radio antenna) can benefit from EMC by using a symmetrical line with two rows of closely spaced vias, as if blocking it from other conductors and creating a coaxial structure in the printed circuit board. However, for such structures, Z 0 is calculated using different formulas.

How can you reduce the cost of a project?
The types of transmission lines described above almost always require the use of a multilayer board, and therefore may not be applicable to the creation of mass-produced low-end products. price category(although at high volumes, 4-layer PCBs are only 20-30% more expensive than double-sided). However, for low-cost projects, line types such as balanced (uniform) or coplanar are also used, which can be constructed on a single-layer board. It should be borne in mind that single-layer types of transmission lines occupy several times more area on the board than microstrip and stripline lines. In addition, while saving on the cost of the printed circuit board, you will be forced to pay more for additional device shielding and noise filtering. A general rule of thumb is that solving EMC problems at the packaging level costs 10-100 times more than solving the same problem at the PCB level.
Therefore, when reducing your design budget by cutting back on the number of PCB layers, be prepared to spend additional time and money on multiple iterations of ordering sample boards to ensure the required level of signal integrity and EMC.

How to reduce the negative effect of changing layers?
According to standard wiring rules, there is at least one decoupling capacitor near each chip, so we can change the layer near the chip. However, the total length of the segments that are not located in the "strip" layer must be taken into account. A rough rule is that the total electrical length of these segments should not exceed one-eighth of the rise time. If too large a change in Z 0 may occur on any of these segments (for example, when using ZIF sockets or other types of sockets for microcircuits), it is better to strive to minimize this length to one tenth of the rise time. Use this rule to determine the maximum allowable total length of non-standardized segments and try to minimize it within these limits as much as possible.
Based on this, for signals with a rise time (according to the documentation) of 2 ns, we must change the layer no further than 10 mm from the center of the microcircuit or from the center of the matching resistor. This rule was developed taking into account a 4-fold margin for the fact that the actual switching time may be significantly less than the maximum according to the documentation. At approximately the same distance (no more) from the place where the layers are changed, there should be at least one decoupling capacitor connecting the corresponding ground and power plans. Such small distances are difficult to achieve when using microcircuits large size, so there are some trade-offs in the layout of modern high-speed circuits. However, this rule justifies the fact that small-sized microcircuits are preferable in high-speed circuits, and explains the fact of the rapid development of BGA and flip-chip technologies, which minimize the signal path from the conductor on the board to the chip chip.

Simulation and testing of prototypes
Due to the availability of many chip options and more more of their application, some engineers may find these rules of thumb to be insufficiently precise, and some will find them exaggerated, but that is the role of “rules of thumb” - they are just rough approximations to intuitively design devices that work correctly.
Nowadays, computer modeling tools are becoming more and more accessible and advanced. They allow you to calculate signal integrity parameters, EMC, depending on the actual layer structure and signal routing. Of course, their use will give more accurate results than our rough approximations, so we recommend using computer simulations as much as possible. However, do not forget that the actual switching time of microcircuits can be significantly shorter than that indicated in the documentation, and this can lead to incorrect results, so make sure that the model of the output and input stages corresponds to reality.
The next step is to check the passage of the critical signal on the first “prototype” sample of the printed circuit board, using a high-frequency oscilloscope. You need to make sure that the waveform is not distorted as it passes through the entire length of the conductor along the printed circuit board, and just following the above rules is unlikely to give an excellent result the first time, although it may be quite good. Using an RF Electromagnetic Field Analyzer, or Emission Spectrum Analyzer, can be another way to examine signal integrity and EMC issues at the "prototype" PCB level. Methods for such analysis are not the topic of this article.
Even if you use complex circuit simulation, don't neglect signal integrity and EMC testing on your very first PCB prototypes.

Providing wave impedances at the PCB manufacturing stage
A typical FR4 material intended for the manufacture of printed circuit boards has a dielectric constant (E r) value of about 3.8...4.2 at 1 GHz. Actual E r values ​​may vary within ±25%. There are FR4 materials that have an E r value that is rated and guaranteed by the supplier and are not much more expensive than conventional materials, but PCB manufacturers are not required to use "rated" FR4 grades unless specifically specified in the PCB order.
PCB manufacturers work with standard dielectric thicknesses (“prepregs” and “laminates”), and their thickness in each layer must be determined before the board is put into production, taking into account thickness tolerances (about ±10%). To ensure a given Z 0, for a certain dielectric thickness, you can select the appropriate conductor width. For some manufacturers it is necessary to indicate the actual required width of the conductor, for others - with a margin for undercuts, which can reach 25-50 microns relative to the nominal width. The best option is to indicate to the manufacturer what width of the conductor in which layers is designed to ensure the specified Z 0 . In this case, the manufacturer can adjust the conductor width and layer structure to ensure the specified parameters in accordance with its production technology. In addition, the manufacturer measures the actual wave impedance on each factory blank and rejects the boards on which Z 0 does not fall within the tolerance of ±10% or more precisely.
For signals above 1 GHz it may be necessary to use more high frequency materials, With better stability and other dielectric parameters (such as Duroid from Rogers, etc.).

Literature
1. Design Techniques for EMC & Signal Integrity, Eur Ing Keith Armstrong.
2. IEC 61188-1-2: 1998 Printed Boards and Printed Board Assemblies - Design and use. Part 1-2: Generic Requirements - Controlled Impedance, www.iec.ch.
3. Design of multilayer printed circuit boards of high complexity. Seminar PCB technology, 2006.
4. http://library.espec.ws/books/chooseant/CHAPTER6/6-1.htm
5. Hardware design. Walt Kester.

Definitions:

Electromagnetic compatibility (EMC): the ability in the process of functioning not to make an excessive contribution to the environment electromagnetic radiation. When this condition is met, all electronic components work together correctly.

Electromagnetic interference (EMI): Electromagnetic energy emitted by one device that may interfere with the performance of another device.

Electromagnetic immunity, EMPU (Electromagnetic immunity, or susceptibility, EMS): tolerance (resistance) to the effects of electromagnetic energy.

Designing for EMC: 4 Key Rules

The problem with rules: the more rules you have, the harder it is to follow them all. The prioritization of their implementation is different.

Suppose, when creating a multilayer printed circuit board, you need to route a high-frequency signal from an analog component to a digital one. Naturally, you want to minimize the likelihood of an electromagnetic compatibility (EMC) problem. After searching the Internet, you find three recommendations that seem to be relevant to your situation:

1. Minimize RF bus lengths
2. Separate the power and ground buses between the analog and digital parts of the circuit
3. Do not break earth polygons with high-frequency conductors

Your vision of three possible options wiring is shown in Fig. 1.

In the first case, the routes are routed directly between the two components, and the ground polygon remains solid. In the second case, a gap is formed in the polygon, and the tracks pass across this gap. In the third case, the routes are laid along the gap in the polygon.

In each of these three cases, one of the above rules is violated. Are these alternative cases equally good because they satisfy two of the three rules? Are they all bad because they each break at least one rule?

These are the questions PCB designers face every day. The right or wrong choice of routing strategy can lead to results in which the board either meets all EMC requirements or has problems with susceptibility to external signals. In this case the choice should be clear, but we'll come back to that later

The problems are reduced after the recommendations are prioritized. Design guidelines are only useful if they are well understood and if they form part of a complete strategy. Once designers learn to prioritize guidelines and understand how those guidelines should be used, they can skillfully design good PCBs.

The following are four main EMC rules based on general features electronics products. In many cases, PCB designers deliberately break one of these rules in an attempt to fulfill more important ones.

Rule 1: Minimize Signal Current Path

This simple rule is present in almost every list of EMC recommendations, but often it is either ignored or downplayed in favor of other recommendations.

Often the PCB designer doesn't even think about where the signal currents flow and prefers to think about signals in terms of voltage, but should be thinking in terms of current.

There are two axioms that every PCB designer should know:

- signal currents always return to their source, i.e. the current path is a loop
- signal currents always use the path with minimal impedance

At frequencies of several megahertz and above, the signal current path is relatively easy to determine because the path with minimum impedance is, in general, the path with minimum inductance. In Fig. Figure 2 shows two components on a printed circuit board. A 50 MHz signal travels along a conductor over the test site from component A to component B.



We know that the same magnitude of signal must propagate back from component B to component A. Let's assume that this current (let's call it return) flows from the terminal of component B, designated GND, to the terminal of component A, also designated GND.

Since the integrity of the polygon is ensured, and the terminals, designated as GND, of both components are located close to each other, this leads to the conclusion that the current will take the shortest path between them (path 1). However, this is not correct. High frequency currents choose the path of least inductance (or the path with the minimum loop area, the path of smallest turn). Most of the signal return current flows through the polygon in a narrow path just below the signal trace (path 2).

If the polygon was made for some reason with a cutout as shown in Figure 3, then cutout 1 would have little effect on signal integrity and emission. Another cutout 2 can lead to significant problems; it conflicts with recommendation 2. The loop area increases significantly; the reverse currents are so intense that they flow along the discontinuity boundary.



At low frequencies (generally kHz and below), the path of lowest impedance tends to be the path with the lowest signal frequency. For a PCB with solid return current polygons, the polygon resistance tends to dissipate the current so that current flowing between two distant points can be spread over a larger area of ​​the board, as shown in Figure 4.



On a mixed-signal board with low-frequency analog and digital components, this can be a problem. Figure 5 illustrates how a well-placed rupture in an earthen landfill can correct the situation by capturing low frequency return currents flowing through the landfill in a designated area.



Rule 2. Do not subdivide the return signal polygon

This is right. We have just shown you an excellent example in a situation where creating a break in the return signal current polygon was the right decision. However, as typical EMC engineers, we advise you never to do this. Why? Because many of the developments we've encountered by well-understood people have been the result of unintentionally breaking Rule 1 and creating gaps in the return polygons. Moreover, the break was often ineffective and unnecessary.

One view is that the analog return signal current should always be isolated from the digital return signal current. This idea originated when analog and digital circuits operated at kilohertz frequencies. For example, boards that were used for digital audio often experienced noise problems due to the influence of low-frequency digital signal currents traveling under the area of ​​the board where sensitive analog amplifiers were located. Some time ago, audio designers tried to avoid this problem by separating return current polygons to control return paths and removing analog current circuits from digital ones.

Our students are asked to solve a design problem that requires protecting sensitive analog components (usually audio amplifiers or phase-locked oscillators) from the digital portion of the circuit by separating the return signal current polygon in such a way that the LF currents are isolated and the HF currents do not generate interference It is usually not obvious how this can be accomplished, and quite often breaks in polygons create more problems than they solve.

A similar situation arises when wiring tires of automobile or aviation electronic equipment. In such equipment, the digital circuit return currents are often isolated from the general enclosure in order to protect the digital circuits from damage by large LF currents that may flow through the metal structure of the vehicle. Filtration electromagnetic interference and transient protection typically require connections to the chassis while the signal must be transmitted relative to the digital return signal bus.

When the chassis circuit and digital return current polygons share the same bus, they appear as a single polygon with a discontinuity. This sometimes creates confusion as to which ground any individual component should be connected to. In this situation, it is usually a good idea to run the chassis bus and digital return on separate buses. The digital return signal polygon must be solid and occupy the area under all digital components, traces and connectors. The connection to the chassis should be limited to the area of ​​the board near the connectors.

Undoubtedly, there are situations where a well-placed break in the return current polygon is required. However, the most reliable method is one continuous polygon for all return signal currents. In cases where a separate low frequency signal susceptible to interference (capable of mixing with other board signals), tracing is used on a separate layer to return this current to the source. In general, never use splitting or cutting in the return signal current polygon. If you are still convinced that a cutout in the polygon is necessary to solve the problem of low-frequency isolation, consult an expert. Do not rely on design recommendations or applications, or try to implement a design that has worked for someone else in a similar design.

Now that we are familiar with the two main rules of EMC, we are ready to revisit the problem in Fig. 1. Which of the alternatives is the best? The first one is the only one that does not contradict the rules. If for some reason (beyond the design desires), a gap in the earthen polygon was required, then the third wiring option is more acceptable. Tracing along the discontinuity minimizes the signal current loop area.

Rule 3: Do not place high-speed circuits between connectors

This is one of the most common problems among the board designs we have reviewed and evaluated in our lab. IN simple boards, which should not have any failures under all EMC requirements without any additional cost or effort, good shielding and filtering were negated because this simple rule was broken.

Why is connector placement so important? At frequencies below several hundred megahertz, the wavelength is on the order of a meter or more. The conductors on the board - possible antennas - have a relatively short electrical length and therefore work inefficiently. However, cables or other devices connected to the board can be quite effective antennas.

Signal currents flowing through conductors and returning through solid polygons create small voltage drops between any two points of the polygon. These voltages are proportional to the current flowing through the polygon. When all connectors are placed on one edge of the board, the voltage drop is negligible.

However, high-speed circuit elements placed between connectors can easily create potential differences between the connectors of several millivolts or more. These voltages can induce excitation currents into connected cables, increasing their emissions.

The board that does everything technical requirements When the connectors are located at one edge, it can be an EMC engineer's nightmare if at least one connector with a cable attached is located on the opposite side of the board. Products that exhibit this type of problem (cables carrying voltages induced through an entire polygon) are particularly difficult to restore to normal. Often this requires fairly good shielding. In many cases, this shielding would be completely unnecessary if the connectors were located on one side or in a corner of the board.

Rule 4. Transition time of the control signal

Board running on clock frequency 100 MHz should never meet the requirements when operating at 2 GHz. A well-shaped digital signal will have a lot of power in the lower harmonics and not as much power in the higher ones. By controlling the signal transition time, it is possible to control the signal power at higher harmonics, which is preferable for EMC. Excessively long transient times can lead to signal integrity problems and thermal problems. During the development and design process, a compromise must be made between these competing necessary conditions. A transient time of approximately 20% of the signal period results in an acceptable waveform, reducing problems caused by crosstalk and radiation. Depending on the application, the transition time may be more or less than 20% of the signal period; however, this time should not be uncontrollable.

There are three main ways to change the edges of digital signals:
- use of digital microcircuits of a series whose performance coincides with the required performance,
- placing a resistor or inductor on the ferrite in series with the output signal, and
- placing a capacitor in parallel with the output signal

The first method is often the simplest and most effective. Using a resistor or ferrite gives the designer more control transition process and has less impact on changes that occur in logical families over time. The advantage of using a control capacitor is that it can be easily removed when not needed. However, it must be remembered that capacitors increase the current of the RF signal source.

Note that trying to filter a single-wire signal in the return current path is always bad idea. For example, never route a low-frequency trace across a gap in the return polygon in an attempt to filter out high-frequency noise. After looking at the first two rules, this should be obvious. However, boards using this incorrect strategy are sometimes identified in our laboratory.

Generally speaking, during the board design and layout process, priorities need to be set to comply with EMC regulations. These rules should not be compromised in attempts to follow other EMC recommendations. However, there are several additional recommendations that are worth considering. For example, it is important to provide adequate power bus separation, keep I/O traces short, and provide filtering for output signals.

It's also a good idea to choose your active devices carefully. Not all pin-compatible semiconductor components are equivalent in terms of noise. Two devices with the same technical parameters, but made by different manufacturers, can differ significantly in the noise they create at the input and output pins, as well as at the power pins. This is especially true for highly integrated chips such as microprocessors and large application-specific integrated circuits (ASICs). It's a good idea to evaluate components from different vendors whenever possible.

Finally, take another look at your design. Even if you are an experienced PCB designer and EMC expert, it is good to have someone who is knowledgeable about EMC analysis and familiar with PCB design. Let him critically examine your design.

Whose advice can you trust? Trust anyone whose recommendations clearly help you fulfill the four main rules. A little extra care during design can save a lot of time, money and effort that would be wasted trying to get an intractable product to work correctly.

Translation of the article:
Dr. Todd Hubing, Dr. Tom Van Doren
Designing for EMC: The TOP 4 GUIDELINES
Printed Circuit Design & Manufacture, June 2003

Dr. Todd Hubing, Professor Emeritus of Electrical Engineering and computer technology, twice awarded the “Best Symposium Publications” prize from the International Symposium of the Institute of Electrical and Electronics Engineers.

Dr. Tom Van Doren, professor of electrical and computer engineering at the Electromagnetic Compatibility Laboratory at the University of Missouri-Rolla.

A little about the "rake" when designing boards.
The most typical error in wiring power circuits in many designs: the blocking capacitances along the “+” and “-” supply lines of the op-amp are thrown onto the ground layer far from each other, that is, the loop current consumption of the op-amp flows through the ground layer. These containers must be positioned so that the distance between the points of their connection to the earthen layer is minimal. High-frequency blocking - SMD capacitors of size 1206 can easily fit under the DIP-8 housing, and with some skill - 1210. Naturally, the area of ​​the resulting current flow circuit should also be minimal, this goes without saying.

Resistors in the power circuits of each IC greatly simplify the wiring, because serve as jumpers and allow the “+” and “-” power supplies to be placed close to each other, which is highly desirable to reduce the emissions of signal/output currents from the power circuits.

There is also an elegant (but very labor-intensive) method for suppressing ground noise without explicitly separating the grounds, especially useful when using double-sided boards - maintaining as much as possible a solid layer of ground on one side (i.e., essentially single-layer circuit routing on the other side , with a minimum of “jumpers”), a thorough analysis of the contours of the flow of power currents along this ground plane and finding equipotential points, i.e. points, the potential difference between which, when currents flow through the ground in the power/load circuits, remains close to zero. These points are used as the “signal” ground pins. The type of current flow contours can be changed, if necessary, by introducing additional cuts or vice versa, by making jumpers in the sections of the earthen layer that arise according to the wiring conditions.

The most detailed study of issues of topology/current flow, etc. was carried out when creating methods for designing devices resistant to EMP pulses arising from the explosion of nuclear weapons or pulsed EMP generators. Unfortunately, publications on this topic are scattered, and moreover, they are often still “under the table.” I scanned one of the illustrative articles, but I can’t attach it here - the limit on the number of attachments has been selected.

About the design of PP.
It should be noted right away that the sometimes straightforward approach - “the more layers the better” - does not work for purely analog (and partly digital) circuits. There are too many factors involved.

Single/double-layer PP on getinax/fiberglass without metallization of holes - are currently adequate only for very simple devices in a large (>>10000) series. The main disadvantages are low reliability under harsh operating conditions (due to detachment of contact pads/conductors during mechanical vibrations and thermal cycles, accumulation of moisture/fluxes through the walls of holes), as well as complexity (and high cost) quality some wiring complex circuits. The installation density is low (usually no more than 3...4 pins per square centimeter of the total board area). The advantage is extreme simplicity and low cost in production (for large volumes and design standards of the order of 0.38 mm - less than $0.3/sq. dm) due to the lack of metallization and the possibility of replacing drilling with punching.

Requirements to increase mounting density while maintaining reliability in the production of BGA packages and portable equipment led to the development of microvia technology, when in addition to the usual (through) via holes on the board on one or both sides, blind via holes are formed (usually with a laser) to the underlying one. layer metallized in one cycle with metallization of through holes. The size of the contact pad for such a transition (0.2...0.3 mm) is much smaller than for a through hole, and the routing in the remaining layers is not disrupted. In addition, in some cases microvia can be placed on the contact pad of an SMD element without the risk of a noticeable part of the solder leaving the hole due to its small size and depth (no more than 0.1...0.15 mm). This greatly increases the wiring density, because As a rule, ordinary vias cannot be placed on the pads of SMD elements. Microvia can also be formed into the inner layers, but this is significantly more difficult and expensive to produce.

A few words about the thickness of copper and the coating of the boards. The main part of the boards is made on materials with foil thicknesses of 35, 18 and 9 microns, while during metallization of the holes on the outer layers, another 15-25 microns of copper are added (there should be ~ 20 microns in the holes). Boards with design standards of 0.127 or less, as a rule, are made on a material with a foil thickness of ~9 microns (the thinner the foil, the less distortion of the shape of the pattern due to lateral undercut of the conductors). There is no need to worry about the “small cross-section of copper”, because Printed conductors, due to good cooling, allow much higher current densities (~ 100 A/sq. mm) than the mounting wire (3...10 A/sq. mm). The final thickness in the outer layers, due to the deposition of copper during metallization of the holes, naturally turns out to be greater than that of the original foil. The resistance of flat conductors depends on their geometry in terms of simple law: square resistance x number of squares. The resistance of a square does not depend on its absolute size, but only on the thickness and conductivity of the material. That is, the resistance of a conductor with a width of 0.25 mm and a length of 10 mm (i.e. 40 squares) is the same as with a width of 2.5 and a length of 100. For 35 micron copper foil this is about 0.0005 Ohm/square. On industrial boards, when metallizing holes, the foil builds up additional layer copper, so the resistance of the square drops by another 20 percent compared to the above. Maintenance, even “fat”, has little effect on the resistance; its purpose is to increase the heat capacity of the conductors so that they do not burn out from a short-term shock current. By using photomask correction (i.e., introducing corrections for undercuts) and anisotropic etching, manufacturers are able to ensure the production of boards with a thickness of the original foil up to 30-40% of the design standards, i.e. when using the thickest foil 105 microns (and taking into account copper deposition - somewhere around 125-130 microns), design standards can be from 0.3...0.35 mm.

A more significant limitation for power circuits is that the permissible current passed through the via hole depends mainly on its diameter, since the thickness of the metallization in it is small (15...25 μm) and, as a rule, does not depend on the thickness of the foil . For a hole with a diameter of 0.5 mm with a board thickness of 1.5 mm, the permissible current is about 0.4 A, for 1 mm - approximately 0.75 A. If it is necessary to pass more current through via holes, a rational solution would be to use not one large, but a set of small via holes, especially if they are dense placement in a “checkerboard” or “honeycomb” pattern - at the vertices of a grid of hexagons. Duplicating vias also provides a benefit in reliability, so it is often used in critical circuits (including signal circuits) when developing equipment for particularly critical applications (for example, life support systems).

Coatings of board conductors can be insulating and/or protective. A “solder mask” is a protective insulating coating in which windows are formed at the contact pads. The conductors can be left copper, or covered with a layer of metal that protects them from corrosion (tin/solder, nickel, gold, etc.). Each type of coating has advantages and disadvantages. Coatings can be thin-layer, a fraction of a micron thick (usually chemical), and thick-layer (galvanic, hot tinning). It is best to apply a solder mask to bare copper or a thin-layer coating; when applied to tinned traces, it holds worse and during soldering a capillary effect appears - solder wicking/mask separation. Gold plating comes in both types, chemical (thin) and galvanic (requiring an electrical connection of conductors, for example, on a connector). In large-scale production, the option of coating pure copper (untinned) contact pads of boards with a flux-like varnish (organic coating) is also popular. The choice of coating type depends on the installation technology and type of parts. For manual installation (and automatic for parts of size 0805 and larger) in the vast majority of cases best option- hot tinning of pads (HASL) with a copper mask. For smaller parts and automatic installation, if there are no requirements for particularly small leaks on the board, one of the best options is chemical (immersion) gold (Flash Gold) or immersion tin. Chemical gold is very cheap in the normal world, the same as hot tinning, and at the same time provides perfectly even seats for elements, without solder tubercles. However, when manufacturing circuit boards in the Russian Federation, it is often better to order coating not with immersion gold, but with tin - its solutions do not save as much. When soldering boards with thin coatings, including Flash Gold, they must be soldered quickly and/or filled with neutral flux to avoid oxidation of copper through the pores of the coating, and when automatically soldering, it is also advisable to use a neutral gas environment (nitrogen, freon).

Below is the most intelligible (in my opinion) literature on this issue, as well as an example of a two-layer computer board for a microprofile meter (profilometer) that I developed about 10 years ago, in which measures to ensure the quality of the topology were applied without fanaticism, only partially. However, this turned out to be enough to provide a resolution of several atoms without any shielding, in a working PC with its noise (and its own power part - control of the commutator motor), many times exceeding the requirements of the technical specifications (the op-amps used are only TL084/LM324). The device was produced until very recently and was the only profilometer of class 1 accuracy in the Russian Federation.

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